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targets/nexys4ddr: fix typo
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Jan 2020 12:17:08 +0000 (13:17 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Jan 2020 12:17:08 +0000 (13:17 +0100)
litex/boards/targets/nexys4ddr.py patch | blob | history

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index b4a4494c23e62bb76f79313b2c6e648f1a9edd01..8940ac4a737612eff2aaf6be4182fdbea5ef44bd 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -79,7 +79,7 @@ class EthernetSoC(BaseSoC):
 
         # Ethernet ---------------------------------------------------------------------------------
         # phy
-        self.submodules.ethphy = LiteEthPHYMII(
+        self.submodules.ethphy = LiteEthPHYRMII(
             clock_pads = self.platform.request("eth_clocks"),
             pads       = self.platform.request("eth"))
         self.add_csr("ethphy")