radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast

PA_SC_AA_CONFIG might be updated when conversative rasterization is
enabled. Because the driver only re-emits the multisample state if
the number of samples is different, that register value might not
be updated correctly.

Found by inspection, doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5850172d127509a960be79a542e82a38b91b4113..c866528d368eeeab7476a3890a321da1f7697b2e 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -865,7 +865,6 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
                              struct radv_pipeline *pipeline)
 {
        int num_samples = pipeline->graphics.ms.num_samples;
-       struct radv_multisample_state *ms = &pipeline->graphics.ms;
        struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 
        if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
@@ -874,17 +873,8 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
        if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
                return;
 
-       radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1);
-       radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
-
        radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
 
-       /* GFX9: Flush DFSM when the AA mode changes. */
-       if (cmd_buffer->device->dfsm_allowed) {
-               radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-               radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
-       }
-
        cmd_buffer->state.context_roll_without_scissor_emitted = true;
 }
 

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index aa97137c7fd696d7941ea6d6074af048b92a67da..63aed7d5042293cd72158150673e7b444bdccb38 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3651,6 +3651,7 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
        radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
        radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
+       radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
 
        /* The exclusion bits can be set to improve rasterization efficiency
         * if no sample lies on the pixel boundary (-8 sample offset). It's
@@ -3660,6 +3661,12 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
                               S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
                               S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
+
+       /* GFX9: Flush DFSM when the AA mode changes. */
+       if (pipeline->device->dfsm_allowed) {
+               radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+               radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
+       }
 }
 
 static void