Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18bf90302b0b2795c3bbee7f4c6b0336da..a0655643ddeada3c1dce31025ef2c25dde201045 100644 (file)
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 449 400 379 316

diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 002b7bba4b77186048c26e77bb456ea86fbb780e..dbc98d0c47ea45a3a51d028dc3ed337bdff9b95b 100644 (file)
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 465 558 589 661

diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index cb336181c8ce3d275b02f22820ef43f9a138ee4e..3b5834e403b5e32eac34cfde0444eff0b7233049 100644 (file)
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 1285 1231 1205 874

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6897aeeb4ce670ae1ef48126b55e0a41a5f8cafb..b9f38126670ce505d76511d51dbc4129d6a12433 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *)
+(* abc_box_id = 22, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
        parameter [15:0] LUT_INIT = 0;
        wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
        assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, lib_whitebox *)
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule