Fix incorrect register mask.

	PR gold/22213
	* sparc.cc (Target_sparc): Fix incorrect register mask.

diff --git a/gold/ChangeLog b/gold/ChangeLog
index 0ac7e9e3a6dc2ea87fc6ed6c63913f376a7d299d..697a40ade1a26313b65c9ab5c6faaf5996d735fe 100644 (file)
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,8 @@
+2017-09-26  Cary Coutant  <ccoutant@gmail.com>
+
+       PR gold/22213
+       * sparc.cc (Target_sparc): Fix incorrect register mask.
+
 2017-09-22  Jim Wilson  <jim.wilson@linaro.org>
 
        * aarch64.cc (Target_aarch64::aarch64_info): Set

diff --git a/gold/sparc.cc b/gold/sparc.cc
index 54c7c334984e62772619888fff43f80e17bcc93e..965d9939aea98ebd1dfcb942285f8dca93ea3a0a 100644 (file)
--- a/gold/sparc.cc
+++ b/gold/sparc.cc
@@ -4164,7 +4164,7 @@ Target_sparc<size, big_endian>::Relocate::relax_call(
   if (op3 != 0x3d)
     {
       // First check RS1
-      reg = (delay_insn >> 14) & 0x15;
+      reg = (delay_insn >> 14) & 0x1f;
       if (reg == 15)
        return;