MEM: Fix master/slave ports in Ruby and non-regression scripts

This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 754a0b79b8f6df6ce229d8db6ac7f63a19ceb540..4c2aeeefefcf0282158b600732ab8b520e69bd07 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -195,8 +195,8 @@ if len(bm) == 2:
         drive_sys.kernel = binary(options.kernel)
     drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
                                ranges = [AddrRange(bm[1].mem())])
-    drive_sys.iobridge.slave = drive_sys.iobus.port
-    drive_sys.iobridge.master = drive_sys.membus.port
+    drive_sys.iobridge.slave = drive_sys.iobus.master
+    drive_sys.iobridge.master = drive_sys.membus.slave
 
     drive_sys.init_param = options.init_param
     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)

diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 28c7dde55e136fe3fa8be22d82ba4aed7f53d078..7f38d543134b0a09016ed023d06a7bd48b087d83 100644 (file)
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -102,7 +102,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
-    system.tester.cpuPort = ruby_port.port
+    system.tester.cpuPort = ruby_port.slave
 
 # -----------------------
 # run simulation

diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 04b99034c7933236a741061dcc66a8b4b40d50ba..869a10ef75b589a07c1504f793e41a33c1fd39d6 100644 (file)
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -125,11 +125,11 @@ for (i, cpu) in enumerate(system.cpu):
     #
     # Tie the cpu ports to the correct ruby system ports
     #
-    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
-    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
     if buildEnv['TARGET_ISA'] == "x86":
-        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
-        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
+        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
         cpu.interrupts.pio = system.piobus.master
         cpu.interrupts.int_master = system.piobus.slave
         cpu.interrupts.int_slave = system.piobus.master

diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 5b693f3f68ca6e717ab9664e83d896c390321021..20c25e833e8cd0a251321b81535b9329e4cd3451 100644 (file)
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -133,7 +133,7 @@ for (i, cpu) in enumerate(cpus):
     #
     # Tie the cpu memtester ports to the correct system ports
     #
-    cpu.test = system.ruby._cpu_ruby_ports[i].port
+    cpu.test = system.ruby._cpu_ruby_ports[i].slave
     cpu.functional = system.funcmem.port
 
     #

diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index 79e6365af097ea92f0faea167d01adf99adc4558..aa93acd2ffd0665d643ff0dc2efa6cc40cbaa270 100644 (file)
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -109,7 +109,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
      #
      # Tie the cpu test ports to the ruby cpu port
      #
-     cpus[i].test = ruby_port.port
+     cpus[i].test = ruby_port.slave
      ruby_port.access_phys_mem = False
 
      i += 1

diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 4074b08f1a44378a59aa1efcf07fef238dfecf4c..5e6d8237259cefb2ff386038531c07a22a0f20de 100644 (file)
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -110,7 +110,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
-    tester.cpuPort = ruby_port.port
+    tester.cpuPort = ruby_port.slave
 
     #
     # Tell each sequencer this is the ruby tester so that it

diff --git a/configs/example/se.py b/configs/example/se.py
index d7b876d466106d136399e1c1ba486a632e2e371a..de98fa0029c74f73f6e5531aae8b6510cfc0cdc5 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -190,8 +190,8 @@ for i in xrange(np):
     system.cpu[i].workload = multiprocesses[i]
 
     if options.ruby:
-        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
-        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
+        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
+        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
 
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 79de421bbdc52e0efdc0a9d95afefd2ac1cbc768..4fdba3c278c93b3df7523b6c05b8feb050eaf1d6 100644 (file)
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         
@@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1

diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 13f4c9c8005cd206d32284015d63573646693357..851001b6f9015348457bc19eeff3782a23d818a3 100644 (file)
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
+        dma_cntrl.dma_sequencer.slave = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1

diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index f6baa402655e6af5d3ab60bee466dbbde13564cc..ac582e4e6808d6e1a22cb8a88a5812617d6006f0 100644 (file)
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -177,9 +177,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1

diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 79e0f15f9e18843d09c178fc44e66ae292112878..20b50e3af4485f815e4fc229c4df939ad5f99d6d 100644 (file)
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -125,7 +125,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -201,9 +201,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index f50315599743be19c90cac3c12c385a107004215..3f89a1a90a171d4f39427cfb5bd3371cd673c7e5 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -118,7 +118,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency
@@ -213,9 +213,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         if options.recycle_latency:

diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index bbe7fe844905d5c7fe374aab8a14a9550ef3b921..768b146775b7317482588403a451de68513f4db9 100644 (file)
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #