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i965: Fix VS URB entry sizing.
authorEric Anholt <eric@anholt.net>
Tue, 26 Oct 2010 21:36:18 +0000 (14:36 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 26 Oct 2010 22:07:10 +0000 (15:07 -0700)
I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1.

Fixes:
glsl-kwin-blur
glsl-max-varying
glsl-routing

src/mesa/drivers/dri/i965/gen6_urb.c patch | blob | history

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index 0a264fcd90ea227495dce80d0491643fd824bfb2..a34123478fb7f8d1a6e697cb7c2abd9e64c0fb15 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -40,7 +40,7 @@ prepare_urb( struct brw_context *brw )
    else
       brw->urb.nr_gs_entries = 0;
    /* CACHE_NEW_VS_PROG */
-   brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1);
+   brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
 
    /* Check that the number of URB rows (8 floats each) allocated is less
     * than the URB space.