whoops, in1_isvec and dec_bi are optional

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index c92214815e6713f8aa827723d5601cb61f0cba89..b620d932d1cc4f08c6be10836aec11cdf000bb51 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -934,9 +934,9 @@ class PowerDecodeSubset(Elaboratable):
             comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
             comb += rm_dec.rc_in.eq(rc_out) # Rc=1
             comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
-            bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
-            comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
-            comb += rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
+            if self.needs_field("imm_data", "in2_sel"):
+                bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
+                comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
 
         # decoded/selected instruction flags
         comb += self.do_copy("data_len", self.op_get("ldst_len"))
@@ -1261,6 +1261,9 @@ class PowerDecode2(PowerDecodeSubset):
                 comb += to_reg.data.eq(fromreg.data)
                 comb += to_reg.ok.eq(fromreg.ok)
 
+        if self.svp64_en:
+            comb += self.rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
+
         # SPRs out
         comb += e.read_spr1.eq(dec_a.spr_out)
         comb += e.write_spr.eq(dec_o.spr_out)