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abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
author
Eddie Hung
<eddie@fpgeh.com>
Mon, 25 May 2020 23:40:53 +0000
(16:40 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Mon, 25 May 2020 23:40:53 +0000
(16:40 -0700)
passes/techmap/abc9_ops.cc
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diff --git
a/passes/techmap/abc9_ops.cc
b/passes/techmap/abc9_ops.cc
index 8d55b18a08f5373820f5cee26489eb5ae538f6c8..16b468b1900c6f236379e2ef5a0136cb7fe19d8f 100644
(file)
--- a/
passes/techmap/abc9_ops.cc
+++ b/
passes/techmap/abc9_ops.cc
@@
-719,8
+719,10
@@
void prep_xaiger(RTLIL::Module *module, bool dff)
bit_users[bit].insert(cell->name);
if (cell->output(conn.first) && !abc9_flop)
- for (auto bit : sigmap(conn.second))
- bit_drivers[bit].insert(cell->name);
+ for (const auto &chunk : conn.second.chunks())
+ if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
+ for (auto b : sigmap(SigSpec(chunk)))
+ bit_drivers[b].insert(cell->name);
}
toposort.node(cell->name);
}