;; The insn will be split in one or several memory moves (movw).
;; [SCz: this does not work ?? So, I switched temporary to 'd' reg]
;;--------------------------------------------------------------------
-(define_insn "movdi"
+(define_expand "movdi"
+ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))
+ (clobber (match_scratch:HI 2 ""))])]
+ ""
+ "
+ /* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_movdi_internal (operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
+")
+
+(define_insn "movdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=U,!u,U,m,m,!u")
(match_operand:DI 1 "general_operand" "iU,iU,!u,mi,!u,!mu"))
(clobber (match_scratch:HI 2 "=&d,&d,&d,&d,&d,&d"))]
"m68hc11_split_move (operands[0], operands[1], operands[2]);
DONE;")
-(define_insn "movdf"
+(define_expand "movdf"
+ [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
+ (match_operand:DF 1 "general_operand" ""))
+ (clobber (match_scratch:HI 2 ""))])]
+ ""
+ "/* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_movdf_internal (operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
+")
+
+(define_insn "movdf_internal"
[(set (match_operand:DF 0 "nonimmediate_operand" "=U,!u,U,m,m,!u")
(match_operand:DF 1 "general_operand" "iU,iU,!u,mi,!u,!mu"))
(clobber (match_scratch:HI 2 "=&d,&d,&d,&d,&d,&d"))]
[(const_int 0)]
"m68hc11_split_move (operands[0], operands[1], operands[2]);
DONE;")
-
+
;;--------------------------------------------------------------------
;;- 32-bit Move Operations.
;; The movsi and movsf patterns are identical except for the mode.
;; pass does not give us a register that dies in the insn and is used
;; for input/output operands.
;;--------------------------------------------------------------------
-(define_insn "movsi"
+(define_expand "movsi"
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (match_operand:SI 1 "general_operand" ""))
+ (clobber (match_scratch:HI 2 ""))])]
+ ""
+ "/* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_movsi_internal (operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
+")
+
+(define_insn "movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=mu,?D,m,?D,?u,?u,!u,D")
(match_operand:SI 1 "general_operand" "imu,im,?D,!u,?D,mi,!u,!D"))
(clobber (match_scratch:HI 2 "=&d,X,X,X,X,&d,&d,X"))]
"m68hc11_split_move (operands[0], operands[1], operands[2]);
DONE;")
-(define_insn "movsf"
+(define_expand "movsf"
+ [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (match_operand:SF 1 "general_operand" ""))
+ (clobber (match_scratch:HI 2 ""))])]
+ ""
+ "/* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_movsf_internal (operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
+")
+
+(define_insn "movsf_internal"
[(set (match_operand:SF 0 "nonimmediate_operand" "=m,D,m,D,!u,!u,!u,D")
(match_operand:SF 1 "general_operand" "im,im,D,!u,D,mi,!u,!D"))
(clobber (match_scratch:HI 2 "=&d,X,X,X,X,&d,&d,X"))]
operands[1] = force_reg (HImode, operands[1]);
}
}
+ /* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
}")
(define_insn "movhi_const0"
operands[1] = force_reg (QImode, operands[1]);
}
}
+ /* For push/pop, emit a REG_INC note to make sure the reload
+ inheritance and reload CSE pass notice the change of the stack
+ pointer. */
+ if (IS_STACK_PUSH (operands[0]) || IS_STACK_POP (operands[1]))
+ {
+ rtx insn;
+
+ insn = emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
+ REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
+ stack_pointer_rtx,
+ REG_NOTES (insn));
+ DONE;
+ }
}")
(define_insn "*movqi_68hc12"