[PATCH][AArch64] Stop redundant zero-extension after UMOV when in DI mode

This patch extends the aarch64_get_lane_zero_extendsi instruction
definition to also cover DI mode. This prevents a redundant AND
instruction from being generated due to the pattern failing to be matched.

Committed on behalf of Sam Tebbs.

gcc/
2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>

	* config/aarch64/aarch64-simd.md
	(*aarch64_get_lane_zero_extendsi<mode>): Rename to...
	(*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>): ... This and
	use GPI iterator instead of SI mode.

gcc/testsuite
2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>

	* gcc.target/aarch64/extract_zero_extend.c: New file.

From-SVN: r263200

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 54cd8f91020f1f3753ae8dd642cc244e19ce70e3..b8152e34c66e8292e2bc5172e4d160becf4661ad 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>
+
+       * config/aarch64/aarch64-simd.md
+       (*aarch64_get_lane_zero_extendsi<mode>): Rename to...
+       (*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>): ... This and
+       use GPI iterator instead of SI mode.
+
 2018-08-01  Richard Earnshaw  <rearnsha@arm.com>
 
        * config/rs6000/rs6000.md (speculation_barrier): Renamed from

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9ee9bbe0b75f493939fb11a8e51ea6890dc08409..1d574cd0fd2799de86177edc6004f6c5a3e674f6 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3030,21 +3030,22 @@
     operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
     return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
   }
-  [(set_attr "type" "neon_to_gp<q>")]
-)
-
-(define_insn "*aarch64_get_lane_zero_extendsi<mode>"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (zero_extend:SI
-         (vec_select:<VEL>
-           (match_operand:VDQQH 1 "register_operand" "w")
-           (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
-  "TARGET_SIMD"
-  {
-    operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
-    return "umov\\t%w0, %1.<Vetype>[%2]";
-  }
-  [(set_attr "type" "neon_to_gp<q>")]
+  [(set_attr "type" "neon_to_gp<q>")]\r
+)\r
+\r
+(define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"\r
+  [(set (match_operand:GPI 0 "register_operand" "=r")\r
+       (zero_extend:GPI\r
+         (vec_select:<VEL>\r
+           (match_operand:VDQQH 1 "register_operand" "w")\r
+           (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]\r
+  "TARGET_SIMD"\r
+  {\r
+    operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,\r
+                                          INTVAL (operands[2]));\r
+    return "umov\\t%w0, %1.<Vetype>[%2]";\r
+  }\r
+  [(set_attr "type" "neon_to_gp<q>")]\r
 )
 
 ;; Lane extraction of a value, neither sign nor zero extension

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c4561cd4594dabb440953a7b6057c3c4e3a1af5a..f9448b94666cccda68f5e9d2936b3ecf50d38d43 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-01  Sam Tebbs  <sam.tebbs@arm.com>
+
+       * gcc.target/aarch64/extract_zero_extend.c: New file.
+
 2018-08-01  Jakub Jelinek  <jakub@redhat.com>
 
        PR c/85704

diff --git a/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c
new file mode 100644 (file)
index 0000000..0209305
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c
@@ -0,0 +1,81 @@
+/* { dg-do compile } */\r
+/* { dg-options "-O3 -fdump-rtl-final" } */\r
+\r
+/* Tests div16qi.  */\r
+typedef unsigned char div16qi __attribute__ ((vector_size (16)));\r
+/* Tests div8qi.  */\r
+typedef unsigned char div8qi __attribute__ ((vector_size (8)));\r
+/* Tests div8hi.  */\r
+typedef unsigned short div8hi __attribute__ ((vector_size (16)));\r
+/* Tests div4hi.  */\r
+typedef unsigned short div4hi __attribute__ ((vector_size (8)));\r
+\r
+/* Tests siv16qi.  */\r
+typedef unsigned char siv16qi __attribute__ ((vector_size (16)));\r
+/* Tests siv8qi.  */\r
+typedef unsigned char siv8qi __attribute__ ((vector_size (8)));\r
+/* Tests siv8hi.  */\r
+typedef unsigned short siv8hi __attribute__ ((vector_size (16)));\r
+/* Tests siv4hi.  */\r
+typedef unsigned short siv4hi __attribute__ ((vector_size (8)));\r
+\r
+\r
+unsigned long long\r
+foo_div16qi (div16qi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned long long\r
+foo_div8qi (div8qi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned long long\r
+foo_div8hi (div8hi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned long long\r
+foo_div4hi (div4hi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned int\r
+foo_siv16qi (siv16qi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned int\r
+foo_siv8qi (siv8qi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned int\r
+foo_siv8hi (siv8hi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+unsigned int\r
+foo_siv4hi (siv4hi a)\r
+{\r
+  return a[0];\r
+}\r
+\r
+/* { dg-final { scan-assembler-times "umov\\t" 8 } } */\r
+/* { dg-final { scan-assembler-not "and\\t" } } */\r
+\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv16qi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv8qi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv8hi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extenddiv4hi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv16qi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv8qi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv8hi" "final" } } */\r
+/* { dg-final { scan-rtl-dump "aarch64_get_lane_zero_extendsiv4hi" "final" } } */\r