arch-arm: make MicroUopSetPCCPSR SerializeAfter

Updating CPSR needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPSR. Otherwise, for example,
the following instructions will access the banked registers from the
previous mode.

The missing IsSerializeAfter had the consequence that the instruction
rfe (return from exception) did not work correctly with the DerivO3CPU
model.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-303

Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24943
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(cherry picked from commit 0d665d4f9893320db4f3b5f7014a6e10c3420b69)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25013
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 251e5c2b9edd90eadad87cb1847b110ac4128f7f..d9eea197e9ec83e58342e39a4af900167a0ecccb 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -691,7 +691,7 @@ let {{
                                          'MicroSetPCCPSR',
                                          {'code': setPCCPSRDecl,
                                           'predicate_test': predicateTest},
-                                         ['IsMicroop'])
+                                         ['IsMicroop', 'IsSerializeAfter'])
 
     header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
                     MicroIntImmDeclare.subst(microAddXiUopIop) + \