Set Verilog source location for explicit blocks (`begin` ... `end`).

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f762f9025f414cbce74707959f92315b071fd8d9..4a5aba79e509d7ab078c16351c49e962fc0bd5a7 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2246,6 +2246,7 @@ behavioral_stmt:
                exitTypeScope();
                if ($4 != NULL && $8 != NULL && *$4 != *$8)
                        frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
+               SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
                delete $4;
                delete $8;
                ast_stack.pop_back();