dev-arm: SMMUv3, enable interrupt interface
authorAdrian Herrera <adrian.herrera@arm.com>
Thu, 10 Dec 2020 18:07:21 +0000 (18:07 +0000)
committerAdrian Herrera <adrian.herrera@arm.com>
Thu, 7 Jan 2021 09:07:09 +0000 (09:07 +0000)
Users can set "irq_interface_enable" to allow software to program
SMMU_IRQ_CTRL and SMMU_IRQ_CTRLACK. This is required to boot Linux v5.4+
in a reasonable time. Notice the model does not implement architectural
interrupt sources, so no assertions will happen.

Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38555
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/SMMUv3.py
src/dev/arm/smmu_v3.cc
src/dev/arm/smmu_v3.hh

index f53b8ecab6d1e5bbc8ab0514962fb0432fd522db..f444d644cbe8530622a9fda7b548fa6d8ab9c285 100644 (file)
@@ -91,6 +91,11 @@ class SMMUv3(ClockedObject):
     reg_map = Param.AddrRange('Address range for control registers')
     system = Param.System(Parent.any, "System this device is part of")
 
+    irq_interface_enable = Param.Bool(False,
+            "This flag enables software to program SMMU_IRQ_CTRL and "
+            "SMMU_IRQ_CTRLACK as if the model implemented architectural "
+            "interrupt sources")
+
     device_interfaces = VectorParam.SMMUv3DeviceInterface([],
                                         "Responder interfaces")
 
index 543a11a623dd74d48772619d2b09e60a39a7f961..3076f5e590aa6ed50b7817725222f6da4a98825c 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@ SMMUv3::SMMUv3(const SMMUv3Params &params) :
     requestPort(name() + ".request", *this),
     tableWalkPort(name() + ".walker", *this),
     controlPort(name() + ".control", *this, params.reg_map),
+    irqInterfaceEnable(params.irq_interface_enable),
     tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy, this),
     configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy, this),
     ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy, this),
@@ -627,6 +628,13 @@ SMMUv3::writeControl(PacketPtr pkt)
             assert(pkt->getSize() == sizeof(uint32_t));
             regs.cr0 = regs.cr0ack = pkt->getLE<uint32_t>();
             break;
+        case offsetof(SMMURegs, irq_ctrl):
+            assert(pkt->getSize() == sizeof(uint32_t));
+            if (irqInterfaceEnable) {
+                warn("SMMUv3::%s No support for interrupt sources", __func__);
+                regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE<uint32_t>();
+            }
+            break;
 
         case offsetof(SMMURegs, cr1):
         case offsetof(SMMURegs, cr2):
index 2d9c1c57e8b6cb753885de6da41691a89492c2c7..e20ab4dc5006485dae626ab708c2438a25e64e62 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@ class SMMUv3 : public ClockedObject
     SMMUTableWalkPort tableWalkPort;
     SMMUControlPort   controlPort;
 
+    const bool irqInterfaceEnable;
+
     ARMArchTLB  tlb;
     ConfigCache configCache;
     IPACache    ipaCache;