Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index c4f91fd9ea3b4a4e2adf4fd9fdbf54609f55f432..461551817e7cd197e1e7850e6d06eecb8e2d60d4 100644 (file)
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -52,8 +52,8 @@ def config_cache(options, system):
                 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                       L1Cache(size = '64kB'))
         if options.l2cache:
-            system.cpu[i].connectMemPorts(system.tol2bus)
+            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
         else:
-            system.cpu[i].connectMemPorts(system.membus)
+            system.cpu[i].connectAllPorts(system.membus)
 
     return system

diff --git a/configs/example/fs.py b/configs/example/fs.py
index e9bc9afb66fdb353bd11609adca0b533094fb1d9..6568f4c8984b3a052098fd55a5b88fc7fe1ee5d7 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -178,7 +178,7 @@ if len(bm) == 2:
     elif buildEnv['TARGET_ISA'] == 'arm':
         drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
-    drive_sys.cpu.connectMemPorts(drive_sys.membus)
+    drive_sys.cpu.connectAllPorts(drive_sys.membus)
     if options.fastmem:
         drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:

diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 8d42b3ab814d6619d64360ab337b722a02ccecc4..200eb191dd269d8256441fdbe796d06167f9086c 100644 (file)
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -218,7 +218,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
                                 L1(size = options.l1size, assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2bus)
+    cpu.connectAllPorts(system.toL2bus, system.membus)
 
 
 # ----------------------

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 0669a7de4bb7f88bbea5f30b4a80ae79dec198b5..de8499ef5198ad88a857c24aca0259fd918474c3 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -150,48 +150,53 @@ class BaseCPU(MemObject):
 
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
-    _mem_ports = []
+    _cached_ports = []
+    if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+        _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+    _uncached_ports = []
     if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
-        _mem_ports = ["itb.walker.port",
-                      "dtb.walker.port",
-                      "interrupts.pio",
-                      "interrupts.int_port"]
+        _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
+
+    def connectCachedPorts(self, bus):
+        for p in self._cached_ports:
+            exec('self.%s = bus.port' % p)
 
-    if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
-        _mem_ports = ["itb.walker.port",
-                      "dtb.walker.port"]
+    def connectUncachedPorts(self, bus):
+        for p in self._uncached_ports:
+            exec('self.%s = bus.port' % p)
 
-    def connectMemPorts(self, bus):
-        for p in self._mem_ports:
-            if p != 'physmem_port':
-                exec('self.%s = bus.port' % p)
+    def connectAllPorts(self, cached_bus, uncached_bus = None):
+        self.connectCachedPorts(cached_bus)
+        if not uncached_bus:
+            uncached_bus = cached_bus
+        self.connectUncachedPorts(uncached_bus)
 
     def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
-        assert(len(self._mem_ports) < 8)
+        assert(len(self._cached_ports) < 7)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
-        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
             if buildEnv['TARGET_ISA'] == 'x86':
                 self.itb_walker_cache = iwc
                 self.dtb_walker_cache = dwc
                 self.itb.walker.port = iwc.cpu_side
                 self.dtb.walker.port = dwc.cpu_side
-                self._mem_ports += ["itb_walker_cache.mem_side", \
-                                    "dtb_walker_cache.mem_side"]
-                self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
+                self._cached_ports += ["itb_walker_cache.mem_side", \
+                                       "dtb_walker_cache.mem_side"]
             elif buildEnv['TARGET_ISA'] == 'arm':
-                self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
         self.toL2Bus = Bus()
-        self.connectMemPorts(self.toL2Bus)
+        self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.l2cache.cpu_side = self.toL2Bus.port
-        self._mem_ports = ['l2cache.mem_side']
+        self._cached_ports = ['l2cache.mem_side']
 
     if buildEnv['TARGET_ISA'] == 'mips':
         CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")

diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index d6db346d4bbd8467ad0c54579d93f8aaad55848c..8e25891e78b33fe61b0218917ea6ac3930ff76c3 100644 (file)
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -46,7 +46,7 @@ class InOrderCPU(BaseCPU):
     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    _cached_ports = ['icache_port', 'dcache_port']
 
     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 38fee369c3ad0d656041a41baa7d8f6139eaabcb..f7602cb86eebc7d4125cb0b3dea88c285ecfc1c2 100644 (file)
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU):
     cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
 
     decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 3d72f4098fe66d3eb61e338b159868421e0ac42b..a4d807f86460c6b3f507bda967f96b8a7ca246f6 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,5 +37,5 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + \
-                    ['icache_port', 'dcache_port', 'physmem_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + \
+                    ['icache_port', 'dcache_port']

diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 6b83c41aafe0243a5854de10a330e4e5bdc68253..8d6888f72e653e2fefbf27cd7d4fcb833583ec98 100644 (file)
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+    _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 10f9e42321bcb5d1850badcf0bc9b6ed7253b6bb..af58cafa59a5657fa996fbd32996a1125a9c353e 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -47,6 +47,6 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index afa46faa5bc8d1dda11c36711dcb005b62a467ab..b14f0e5b1f3e328e1d9e74a85157a944e9b9e3dc 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -40,7 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
+    cpu.connectAllPorts(system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index b5c720ddaa4e5af3a2fc2258692fd1871a44678b..5c770cdbc967bee76d50a892f61c7884737b58fe 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -72,7 +72,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 40d90623a4dd77a92ce1bec39960215395ff158b..07851ae9f1082718fee0c9f60465c12ae1ccc62d 100644 (file)
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -41,6 +41,6 @@ system = System(cpu = cpu,
                 physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 563772213f7d22dca4d36f8b65a7fdbc3370739e..a4c054122e1079d80e323b78b28ca7f24c7de86f 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -46,6 +46,6 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system = system)

diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 543cb2419cb3c6c0c178149bc8a884c863d45b7b..c20a67df72e823750ba5f4113ac3b17f93f2bd70 100644 (file)
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index b9d00c1eefdf4d4b90244662b3f087f9be4cd82f..a1e363447fe11dfd38c855260667c2e8e6c8ed53 100644 (file)
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 570a1766a5b8c02b2cf493cbefaf6d54861e8e26..705f13ef391965add85571a1d996590808c61fad 100644 (file)
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -41,7 +41,7 @@ system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 # add L1 caches
 for cpu in cpus:
-    cpu.connectMemPorts(system.membus)
+    cpu.connectAllPorts(system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 75ffefd0828bb6c889e98c38de6ba8e7eae31804..d88a9b395f2a737eef8aa2fcbe233381f4e47c78 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -71,7 +71,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index cc303886b9ef8a9c322d4b1796bdd88361b5971c..4a2efcc577f54975c07787c58ff7fa1bd9e7f1c8 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -33,7 +33,7 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
+system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
 root = Root(system = system)

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 7a8da70bbf2c0147e1290090897d6ed33d9b365c..f5793b282879c07d43bebcf167d607455eb6becd 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -71,7 +71,7 @@ for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectMemPorts(system.toL2Bus)
+    cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
 
 # connect memory to membus

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 0ed985a17dbcbdf8b13189282f7509bb159ad832..739e11e5547e79c3274e32417de98822925ea4c4 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -43,7 +43,7 @@ system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system = system)

diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 35b329f5782a78658dfc2d20d307f1858badda74..ae2c59110fea4307aa1966f6e2b1b724986afd21 100644 (file)
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -34,7 +34,7 @@ import FSConfig
 cpu = AtomicSimpleCPU(cpu_id=0)
 system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 
 root = Root(system=system)
 

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index d19dc9c261c557dbe80fdba0ddd7d0f730d5ba2e..7744560f9985139033cb97ec2d02529fd77072de 100644 (file)
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -92,7 +92,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 9b52cd92be8288d44c69aba60163a378679da7f5..fd2d6643134643c77257cda872e19b085c436320 100644 (file)
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index d78a09db458f6e6312d81b72557869cf107263b5..9d3dbaa918738bbfdca0994ddd48fff6d9128c7f 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -90,7 +90,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index cfc619b061b95d12b833dc0c72286598b4b23978..cbacf1995ea2a899d1530265baf9bfe21ea51d3b 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 13b7bf32eec8ac8303f5578c69a5cb802c4d44a7..f0105461d55a2850a767fba1f24d123bda67f132 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -90,7 +90,7 @@ for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
     # connect cpu level-1 caches to shared level-2 cache
-    c.connectMemPorts(system.toL2Bus)
+    c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 0c398462881cf1dd7c5f01fece99cd0abc3ba371..9a262b3b228e49b2d0afa3f9bcad9f279459edd0 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
 # connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system=system)

diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index ce191930ea7f635d603d1d3b1949061fb6d35def..7c6fde7c329abbe0a72e13bdacb9dd15be329f3f 100644 (file)
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -35,12 +35,12 @@ from Benchmarks import *
 test_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-stream-client.rcS'))
 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-test_sys.cpu.connectMemPorts(test_sys.membus)
+test_sys.cpu.connectAllPorts(test_sys.membus)
 
 drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-drive_sys.cpu.connectMemPorts(drive_sys.membus)
+drive_sys.cpu.connectAllPorts(drive_sys.membus)
 
 root = makeDualRoot(test_sys, drive_sys, "ethertrace")