#include "obstack.h"
#include "expr.h"
+#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
+#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
+
+
static rtx add_constant ();
int pragma_interrupt;
struct rtx_def *table_lab;
enum attr_cpu sh_cpu; /* target cpu */
+
+char *max_si;
+char *max_hi;
+int max_count_si;
+int max_count_hi;
+
/* Global variables for machine-dependent things. */
/* Saved operands from the last compare to use when we generate an scc
'!' dump the constant table
'#' output a nop if there is nothing to put in the delay slot
'@' print rte or rts depending upon pragma interruptness
- 'R' print the next register or memory location along, ie the lsw in
- a double word value
+ 'R' print the LSW of a dp value - changes if in little endian
+ 'T' print the next word of a dp value - same as 'R' in big endian mode.
+ 'S' print the MSW of a dp value - changes if in little endian
'O' print a constant without the #
'M' print a constant as its negative
'N' print insides of a @++ or @-- o */
fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], (stream));
break;
case 'R':
- /* Next location along in memory or register */
+ /* LSW of a double */
+ switch (GET_CODE (x))
+ {
+ case REG:
+ fputs (reg_names[REGNO (x) + LSW], (stream));
+ break;
+ case MEM:
+ print_operand_address (stream, XEXP (adj_offsettable_operand (x, LSW *4), 0));
+ break;
+ }
+ break;
+ case 'T':
+ /* Next word of a double */
switch (GET_CODE (x))
{
case REG:
fputs (reg_names[REGNO (x) + 1], (stream));
break;
case MEM:
- print_operand_address (stream, XEXP (adj_offsettable_operand (x, 4), 0));
+ print_operand_address (stream, XEXP (adj_offsettable_operand (x,1 *4), 0));
+ break;
+ }
+ break;
+ case 'S':
+ /* MSW of a double */
+ switch (GET_CODE (x))
+ {
+ case REG:
+ fputs (reg_names[REGNO (x) + MSW], (stream));
+ break;
+ case MEM:
+ print_operand_address (stream, XEXP (adj_offsettable_operand (x, MSW *4), 0));
break;
}
break;
&& GET_CODE (XEXP (dst, 0)) == POST_INC)
{
operands[0] = XEXP (XEXP (dst, 0), 0);
- return "mov.l %R1,@(4,%0)\n\tmov.l %1,@%0\n\tadd #8,%0";
+ return "mov.l %T1,@(4,%0)\n\tmov.l %1,@%0\n\tadd #8,%0";
}
if (register_operand (dst, mode)
&& register_operand (src, mode))
{
if (REGNO (src) == MACH_REG)
- return "sts mach,%0\n\tsts macl,%R0";
+ return "sts mach,%S0\n\tsts macl,%R0";
/*
when mov.d r1,r2 do r2->r3 then r1->r2
*/
if (REGNO (src) + 1 == REGNO (dst))
- return "mov %R1,%R0\n\tmov %1,%0 ! cra";
+ return "mov %T1,%T0\n\tmov %1,%0 ! cra";
else
- return "mov %1,%0\n\tmov %R1,%R0 ! crb";
+ return "mov %1,%0\n\tmov %T1,%T0 ! crb";
}
else if (GET_CODE (src) == CONST_INT)
{
HOST_WIDE_INT val = INTVAL (src);
int rn = REGNO (operands[0]);
+ int msw = rn + MSW;
+ int lsw = rn + LSW;
if (val < 0)
{
- fprintf (asm_out_file, "\tmov #-1,r%d\n", rn);
+ fprintf (asm_out_file, "\tmov #-1,r%d\n", msw);
}
else
{
- fprintf (asm_out_file, "\tmov #0,r%d\n", rn);
+ fprintf (asm_out_file, "\tmov #0,r%d\n", msw);
}
- fprintf (asm_out_file, "\tmov #%d,r%d\n", val, rn + 1);
+ fprintf (asm_out_file, "\tmov #%d,r%d\n", val, lsw);
return "";
}
else if (GET_CODE (src) == MEM)
}
else if (GET_CODE (inside) == LABEL_REF)
{
- return "mov.l %1,%0\n\tmov.l %1+4,%R0";
+ return "mov.l %1,%0\n\tmov.l %1+4,%T0";
}
else if (GET_CODE (inside) == POST_INC)
{
- return "mov.l %1,%0\n\tmov.l %1,%R0 !mdi\n";
+ return "mov.l %1,%0\n\tmov.l %1,%T0 !mdi\n";
}
else
abort ();
if (dreg == ptrreg1)
{
/* Copy into the second half first */
- return "mov.l %R1,%R0\n\tmov.l %1,%0 ! cr";
+ return "mov.l %T1,%T0\n\tmov.l %1,%0 ! cr";
}
}
- return "mov.l %1,%0\n\tmov.l %R1,%R0";
+ return "mov.l %1,%0\n\tmov.l %T1,%T0";
}
/* Emit assembly to shift reg by k bits */
fprintf (file, term);
fprintf (file, "! %d %d\n", max_count_si, max_count_hi);
+
+ if (TARGET_LITTLE_ENDIAN)
+ fprintf (file, "\t.little\n");
}
void
data_section ();
- pos = fprintf (file, "\n! Hitachi SH cc1 (%s) (release I-1) arguments:", version_string);
+ pos = fprintf (file, "\n! Hitachi SH cc1 (%s) arguments:", version_string);
output_options (file, f_options, f_len, W_options, W_len,
pos, 75, " ", "\n! ", "\n\n");
}
\f
+/* Actual number of instructions used to make a shift by N */
+char ashiftrt_insns[] = { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
+char lshiftrt_insns[] = { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,4,5,1,2,2,3,3,4,4,5,2,3,3,4,4,5,5,6};
+char shift_insns[] = { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,4,5,1,2,2,3,3,4,4,5,2,3,3,4,4,5,5,6};
+
+int
+shiftinsns (shift, n)
+enum rtx_code shift;
+int n;
+{
+ switch (shift)
+ {
+ case ASHIFTRT:
+ return ashiftrt_insns[n];
+ case LSHIFTRT:
+ return lshiftrt_insns[n];
+ case ASHIFT:
+ return shift_insns[n];
+ default:
+ abort();
+ }
+}
+
+
/* Return the cost of a shift */
rtx RTX;
{
/* If shift by a non constant, then this will be expensive. */
- if (GET_CODE (XEXP (RTX, 1)) != CONST_INT)
- return 20;
+ if (GET_CODE (XEXP (RTX, 1)) != CONST_INT)
+ {
+ return 20;
+ }
/* otherwise, it will be very cheap if by one of the constants
we can cope with. */
+
if (CONST_OK_FOR_K (INTVAL (XEXP (RTX, 1))))
return 1;
-
/* otherwise it will be several insns, but we pretend that it will be more than
just the components, so that combine doesn't glue together a load of shifts into
one shift which has to be emitted as a bunch anyway - breaking scheduling */
rtx wrk = gen_reg_rtx (SImode);
rtx t;
char *func;
+
if (GET_CODE (operands[2]) == CONST_INT)
{
int value = INTVAL (operands[2]);
top:
+
switch (code)
{
case ASHIFTRT:
value = -value;
goto top;
}
-
+ if (value == 31)
+ {
+ emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
+ return 1;
+ }
+ else if (value >= 16 && value <= 19)
+ {
+ emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
+ value -= 16;
+ while (value --)
+ gen_ashift (ASHIFTRT,1, wrk);
+ emit_move_insn (operands[0], wrk);
+ return 1;
+ }
/* Expand a short sequence inline, longer call a magic routine */
if (value <= 5)
{
}
}
+
return 0;
}
}
+/* Returns 1 if OP is a valid count operand for a shift operation. */
+int
+shiftby_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ if (immediate_operand (op, mode))
+ return 1;
+ return 0;
+}
+
/* Returns 1 if OP is a valid source operand for a logical operation. */
int
return 0;
}
+
+
/* Turn this on to recognise shift insns which aren't supported in the
hardware. This will allow the combiner to notice more patterns,
but the down side is that the asm outputter will have to emit
{
return 0;
}
+
#define SDB_DELIM ";"
+#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
+
#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
+#define ASM_SPEC "%{ml:-little}"
+
+#define LINK_SPEC "%{ml:-m shl}"
+
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
#define BSR_BIT (1<<26)
#define SHORTADDR_BIT (1<<27)
#define PACKSTRUCT_BIT (1<<28)
+#define LITTLE_ENDIAN_BIT (1<<29)
/* Nonzero if we should generate code using type 0 insns */
#define TARGET_SH0 (target_flags & SH0_BIT)
/* Nonzero if packing structures as small as they'll go (incompatible with Hitachi's compiler) */
#define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT)
-#define TARGET_SWITCHES \
-{ {"isize", ( ISIZE_BIT) }, \
- {"space", ( SPACE_BIT) }, \
- {"0", ( SH0_BIT) }, \
- {"1", ( SH1_BIT) }, \
- {"2", ( SH2_BIT) }, \
- {"3", ( SH3_BIT) }, \
- {"ac", ( MAC_BIT) }, \
- {"dalign", ( DALIGN_BIT) }, \
- {"c", ( C_BIT) }, \
- {"r", ( RTL_BIT) }, \
- {"bigtable", ( BIGTABLE_BIT)}, \
- {"try-r0", ( TRYR0_BIT)}, \
- {"R", ( R_BIT) }, \
- {"nosave", ( NOSAVE_BIT) }, \
- {"clen3", ( CONSTLEN_3_BIT) }, \
- {"clen0", ( CONSTLEN_0_BIT) }, \
- {"smallcall", ( SMALLCALL_BIT) }, \
- {"hitachi", ( HITACHI_BIT) }, \
- {"paranoid", ( PARANOID_BIT) }, \
- {"r2", ( RETR2_BIT) }, \
- {"shortaddr", ( SHORTADDR_BIT) }, \
- {"bsr", ( BSR_BIT) }, \
- {"packstruct",( PACKSTRUCT_BIT) }, \
- {"", TARGET_DEFAULT} \
+
+#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
+
+#define TARGET_SWITCHES \
+{ {"0", (SH0_BIT) }, \
+ {"1", (SH1_BIT) }, \
+ {"2", (SH2_BIT) }, \
+ {"3", (SH3_BIT) }, \
+ {"3l", (SH3_BIT|LITTLE_ENDIAN_BIT)}, \
+ {"R", (R_BIT) }, \
+ {"ac", (MAC_BIT) }, \
+ {"b", (-LITTLE_ENDIAN_BIT) }, \
+ {"bigtable", (BIGTABLE_BIT)}, \
+ {"bsr", (BSR_BIT) }, \
+ {"c", (C_BIT) }, \
+ {"clen0", (CONSTLEN_0_BIT) }, \
+ {"clen3", (CONSTLEN_3_BIT) }, \
+ {"dalign", (DALIGN_BIT) }, \
+ {"hitachi", (HITACHI_BIT) }, \
+ {"isize", (ISIZE_BIT) }, \
+ {"l", (LITTLE_ENDIAN_BIT) }, \
+ {"nosave", (NOSAVE_BIT) }, \
+ {"packstruct",(PACKSTRUCT_BIT) }, \
+ {"paranoid", (PARANOID_BIT) }, \
+ {"r", (RTL_BIT) }, \
+ {"r2", (RETR2_BIT) }, \
+ {"shortaddr", (SHORTADDR_BIT) }, \
+ {"smallcall", (SMALLCALL_BIT) }, \
+ {"space", (SPACE_BIT) }, \
+ {"try-r0", (TRYR0_BIT)}, \
+ {"", TARGET_DEFAULT} \
}
+
#define TARGET_DEFAULT (FAST_BIT)
+
/* Macro to define table for command options with values. */
#define TARGET_OPTIONS \
{ { "maxsi-", &max_si}, \
{ "maxhi-", &max_hi} }
+
#define OVERRIDE_OPTIONS \
do { \
sh_cpu = CPU_SH0; \
sh_cpu = CPU_SH1; \
if (TARGET_SH2) \
sh_cpu = CPU_SH2; \
- if (TARGET_SH3) \
- sh_cpu = CPU_SH3; \
+ if (TARGET_SH3) \
+ sh_cpu = CPU_SH3|CPU_SH2; \
\
/* We *MUST* always define optimize since we *HAVE* to run \
shorten branches to get correct code. */ \
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
+
#define BITS_BIG_ENDIAN 0
+
/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN 1
+#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
/* Define this if most significant word of a multiword number is the lowest
numbered. */
-#define WORDS_BIG_ENDIAN 1
+#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+
+
+/* Define this to set the endianness to use in libgcc2.c, which can
+ not depend on target_flags. */
+#if defined(__LITTLE_ENDIAN__)
+#define LIBGCC2_WORDS_BIG_ENDIAN 0
+#else
+#define LIBGCC2_WORDS_BIG_ENDIAN 1
+#endif
/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8
case UDIV: \
case MOD: \
case UMOD: \
- return COSTS_N_INSNS (100); \
+ return COSTS_N_INSNS (20); \
case FLOAT: \
case FIX: \
return 100;
extern int pragma_interrupt;
#define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16)
-char *max_si;
-char *max_hi;
-int max_count_si;
-int max_count_hi;
+extern char *max_si;
+extern char *max_hi;
+extern int max_count_si;
+extern int max_count_hi;
;; %* -- print a local label
;; %^ -- increment the local label number
;; %# -- output a nop if there is nothing to put in the delay slot
-;; %R -- print the next register or memory location along, ie the lsw in
-;; a double word value
+;; %R -- print the lsw arg of a double,
+;; %S -- print the msw arg of a double
;; %O -- print a constant without the #
;; %M -- print a constant as its negative
;;
;; (define_function_unit {name} {num-units} {n-users} {test}
;; {ready-delay} {issue-delay} [{conflict-list}])
-(define_function_unit "memory" 1 0 (eq_attr "type" "load,pcloadsi,pcloadhi") 2 0)
-(define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 3 0)
-(define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 5 0)
+(define_function_unit "memory" 1 0 (eq_attr "type" "load,pcloadsi,pcloadhi") 2 2)
+(define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 7 7)
+(define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 9 9)
(define_attr "needs_delay_slot" "yes,no"
(cond [(eq_attr "type" "jump") (const_string "yes")
(define_delay
(and (eq_attr "type" "cbranch")
- (eq_attr "cpu" "sh2"))
+ (eq_attr "cpu" "sh2,sh3"))
[(eq_attr "in_delay_slot" "yes") (nil) (nil)])
(define_attr "in_delay_slot" "maybe,yes,no"
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 18))]
""
- "clrt\;addc %R2,%R0\;addc %2,%0"
+ "clrt\;addc %R2,%R0\;addc %S2,%S0"
[(set_attr "length" "6")])
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 18))]
""
- "clrt\;subc %R2,%R0\;subc %2,%0"
+ "clrt\;subc %R2,%R0\;subc %S2,%S0"
[(set_attr "length" "6")])
(define_insn "subsi3"
"TARGET_SH2"
"")
+
(define_insn ""
[(set (reg:DI 20)
(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
- "TARGET_SH2"
+ "(TARGET_SH2) && 0"
"dmuls.l %2,%1"
[(set_attr "type" "dmpy")])
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
(set (match_operand:DI 0 "arith_reg_operand" "=r")
(reg:DI 20))]
- "TARGET_SH2"
+ "(TARGET_SH2) && 0"
"")
(define_insn ""
[(set (reg:DI 20)
(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
- "TARGET_SH2"
+ "(TARGET_SH2) && 0"
"dmulu.l %2,%1"
[(set_attr "type" "dmpy")])
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
(set (match_operand:DI 0 "arith_reg_operand" "=r")
(reg:DI 20))]
- "TARGET_SH2"
+ "(TARGET_SH2) && 0"
"")
\f
;;
;; shift left
+
+
(define_insn "ashlsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
(define_expand "ashlsi3"
[(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
- (match_operand:SI 2 "immediate_operand" "")))
+ (match_operand:SI 2 "shiftby_operand" "")))
(clobber (reg:SI 18))])]
""
"if (gen_shifty_op (ASHIFT, operands)) DONE; else FAIL;")
"shar %0"
[(set_attr "type" "arith")])
-(define_insn "ashrsi3_16"
- [(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")))
- (clobber (reg:SI 18))]
- "INTVAL(operands[2]) == 16"
- "shlr16 %0\;exts.w %0,%0"
- [(set_attr "type" "arith")
- (set_attr "length" "4")])
; an arithmetic shift right by 16 is better as a logical shift and a
; sign extend
; (set (match_dup 0) (sign_extend:SI (subreg:HI (match_dup 3) 0)))]
; "operands[3] = gen_reg_rtx (SImode);")
+(define_insn "ashrsi2_16"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (const_int 16)))
+ (clobber (reg:SI 18))]
+ ""
+ "shlr16 %0\;exts.w %0,%0"
+ [(set_attr "length" "4")])
+
+
+(define_insn "ashrsi2_31"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (const_int 31)))]
+ ""
+ "shal %0\;subc %0,%0"
+ [(set_attr "length" "4")])
+
+
(define_insn "ashrsi3_n"
[(set (reg:SI 4)
(ashiftrt:SI (reg:SI 4)
; logical shift right
;
+
(define_insn "lshrsi3_k"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
(define_expand "lshrsi3"
[(parallel[(set (match_operand:SI 0 "arith_reg_operand" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
- (match_operand:SI 2 "immediate_operand" "")))
+ (match_operand:SI 2 "shiftby_operand" "")))
(clobber (reg:SI 18))])]
""
"if (gen_shifty_op (LSHIFTRT, operands)) DONE; else FAIL;")
(const_int 1)))
(clobber (reg:SI 18))]
""
- "shll %R0\;rotcl %0"
+ "shll %R0\;rotcl %S0"
[(set_attr "length" "4")])
(define_expand "ashldi3"
(const_int 1)))
(clobber (reg:SI 18))]
""
- "shlr %0\;rotcr %R0"
+ "shlr %S0\;rotcr %R0"
[(set_attr "length" "4")])
(define_expand "lshrdi3"
(const_int 1)))
(clobber (reg:SI 18))]
""
- "shar %0\;rotcr %R0"
+ "shar %S0\;rotcr %R0"
[(set_attr "length" "4")])
(define_expand "ashrdi3"
;; -------------------------------------------------------------------------
(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
- (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "0,r")))
+ [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+ (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
(clobber (reg:SI 18))]
""
- "@
- mov %1,%0\;shll %0\;subc %0,%0 ! b sidi2
- mov %1,%0\;mov %1,%R0\;shll %0\;subc %0,%0 ! a sidi2"
- [(set_attr "length" "6,8")])
+ "mov %1,%S0\;mov %1,%R0\;shll %S0\;subc %S0,%S0 ! a sidi2"
+ [(set_attr "length" "8")])
(define_insn "extendhisi2"
[(set (match_operand:SI 0 "arith_reg_operand" "=r,z,r")
- (sign_extend:SI (match_operand:HI 1 "arith_operand" "r,u,m")))]
+ (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,u,m")))]
""
"@
exts.w %1,%0
[(set (match_operand:DI 0 "push_operand" "=<")
(match_operand:DI 1 "arith_reg_operand" "r"))]
""
- "mov.l %R1,%0\;mov.l %1,%0"
+ "mov.l %T1,%0\;mov.l %01,%0"
[(set_attr "length" "4")
(set_attr "type" "store")])
[(set (match_operand:DF 0 "push_operand" "=<")
(match_operand:DF 1 "arith_reg_operand" "r"))]
""
- "mov.l %R1,%0\;mov.l %1,%0"
+ "mov.l %T1,%0\;mov.l %1,%0"
[(set_attr "length" "4")
(set_attr "type" "store")])
;; Misc insns
;; ------------------------------------------------------------------------
-(define_insn "dect"
- [(parallel[
- (set (reg:SI 18)
- (eq:SI (match_operand:SI 0 "register_operand" "=r")
- (const_int 1)))
-
- (set (match_dup 0)
- (plus:SI (match_dup 0)
- (const_int -1)))])]
- "TARGET_SH2"
- "dt %0")
+;(define_insn "dect"
+; [(parallel[
+; (set (match_dup 0)
+; (plus:SI (match_dup 0)
+; (const_int -1)))
+;
+; (set (reg:SI 18)
+; (eq:SI (match_operand:SI 0 "register_operand" "=r")
+; (const_int 0)))])]
+; "TARGET_SH2"
+; "dt %0")
(define_insn "nop"
[(const_int 0)]
+
+
+(define_peephole
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 0)
+ (const_int -1)))
+ (set (reg:SI 18)
+ (eq:SI (match_dup 0)
+ (const_int 0)))]
+ "TARGET_SH2"
+ "dt %0")
+
+
+
+
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+MULTILIB_OPTIONS=ml
+MULTILIB_DIRNAMES=ml
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
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