Change the way the hierarchy is separated. Now all virtual functions are in the inter...

cpu/simple_cpu/simple_cpu.cc:
    Switch doEvents to doEvents()

--HG--
extra : convert_revision : 14b9517017e76c7b941247004393bf260f397d9a

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index adbd17a35f8fe41b6b3af4695d307f2217cba03c..0d5fc4077085ee5afd931a4ebf451e106d6ef70e 100644 (file)
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -349,7 +349,7 @@ SimpleCPU::read(Addr addr, T& data, unsigned flags)
         // Ugly hack to get an event scheduled *only* if the access is
         // a miss.  We really should add first-class support for this
         // at some point.
-        if (result != MA_HIT && dcacheInterface->doEvents) {
+        if (result != MA_HIT && dcacheInterface->doEvents()) {
             memReq->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
             unscheduleTickEvent();
@@ -432,7 +432,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         // Ugly hack to get an event scheduled *only* if the access is
         // a miss.  We really should add first-class support for this
         // at some point.
-        if (result != MA_HIT && dcacheInterface->doEvents) {
+        if (result != MA_HIT && dcacheInterface->doEvents()) {
             memReq->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
             unscheduleTickEvent();
@@ -635,7 +635,7 @@ SimpleCPU::tick()
             // Ugly hack to get an event scheduled *only* if the access is
             // a miss.  We really should add first-class support for this
             // at some point.
-            if (result != MA_HIT && icacheInterface->doEvents) {
+            if (result != MA_HIT && icacheInterface->doEvents()) {
                 memReq->completionEvent = &cacheCompletionEvent;
                 lastIcacheStall = curTick;
                 unscheduleTickEvent();