freedreno/a6xx: fix MSAA resolve hangs
authorRob Clark <robdclark@chromium.org>
Wed, 24 Jul 2019 20:31:13 +0000 (13:31 -0700)
committerRob Clark <robdclark@chromium.org>
Mon, 29 Jul 2019 22:15:31 +0000 (15:15 -0700)
Seems like RB_BLIT_SCISSOR needs to be aligned to (minimum?) tile size.

Fixes intermittent GPU hangs triggered by some of the three.js samples
on https://threejs.org/

Signed-off-by: Rob Clark <robdclark@chromium.org>
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c

index 27c57a0074cdce5c03e87bca5d00276364ba6fd6..f93dd5709820771e6a7d07b49ad81f64559e077c 100644 (file)
@@ -679,17 +679,10 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
        struct pipe_scissor_state blit_scissor;
        struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 
-       blit_scissor.minx = batch->max_scissor.minx;
-       blit_scissor.miny = batch->max_scissor.miny;
-       blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
-       blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
-
-       /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
-        * small render targets.  But since we align pitch to binw I think
-        * we can get away avoiding GPU hangs a simpler way, by just rounding
-        * up the blit scissor:
-        */
-       blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
+       blit_scissor.minx = 0;
+       blit_scissor.miny = 0;
+       blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
+       blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
 
        OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
        OUT_RING(ring,