ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.

diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa
index d87374069237793df29fed7236e2cf5bc9657d14..d62559b6987af9f61fcae52a4556a6200008dd3d 100644 (file)
--- a/src/arch/arm/isa/thumbdecode.isa
+++ b/src/arch/arm/isa/thumbdecode.isa
@@ -311,7 +311,44 @@
         }
         0x2: decode LTOPCODE_15 {
             0x0: decode HTOPCODE_9 {
-                0x0: WarnUnimpl::Data_processing_modified_immediate();
+                0x0: decode HTOPCODE_8_5 {
+                    0x0: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: WarnUnimpl::tst(); // mod imm
+                        }
+                        default: WarnUnimpl::and(); // mod imm
+                    }
+                    0x1: WarnUnimpl::bic(); // mod imm
+                    0x2: decode HTRN {
+                        0xf: WarnUnimpl::mov(); // mod imm
+                        default: WarnUnimpl::orr(); // mod imm
+                    }
+                    0x3: decode HTRN {
+                        0xf: WarnUnimpl::mvn(); // mod imm
+                        default: WarnUnimpl::orn(); // mod imm
+                    }
+                    0x4: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: WarnUnimpl::teq(); // mod imm
+                        }
+                        default: WarnUnimpl::eor(); // mod imm
+                    }
+                    0x8: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: WarnUnimpl::cmn(); // mod imm
+                        }
+                        default: WarnUnimpl::add(); // mod imm
+                    }
+                    0xa: WarnUnimpl::adc(); // mod imm
+                    0xb: WarnUnimpl::sbc(); // mod imm
+                    0xd: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: WarnUnimpl::cmp(); // mod imm
+                        }
+                        default: WarnUnimpl::sub(); // mod imm
+                    }
+                    0xe: WarnUnimpl::rsb(); // mod imm
+                }
                 0x1: WarnUnimpl::Data_processing_plain_binary_immediate();
             }
             0x1: WarnUnimpl::Branches_and_miscellaneous_control();