(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 828e329059af63f3a5c83f533587e8ccfde0394a..5090342821fd9f0730182f7d8072355eb2694d3b 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -77,8 +77,8 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 |6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
-|/ | / |RG 0 | 0 | dz  sz  | simple mode                      |
-|/ | / |RG 0 | 1 | dz  sz  | scalar reduce mode (mapreduce) |
+|/ | / |0  0 |RG | dz  sz  | simple mode                      |
+|/ | / |1  0 |RG | dz  sz  | scalar reduce mode (mapreduce) |
 |zz|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode      |
 |/ |SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |