return 0;
}
+static inline int S_FIXED(float value, unsigned frac_bits)
+{
+ return value * (1 << frac_bits);
+}
+
static void
radv_init_sampler(struct radv_device *device,
struct radv_sampler *sampler,
#include "util/debug.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
-#include "main/menums.h"
struct radv_blend_state {
uint32_t blend_enable_4bit;
#include "util/macros.h"
#include "util/list.h"
#include "util/xmlconfig.h"
-#include "main/macros.h"
#include "vk_alloc.h"
#include "vk_debug_report.h"
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
-#include "main/macros.h"
+#include <string.h>
#include "amd_family.h"
+#include "util/u_memory.h"
+#include "util/u_math.h"
struct radeon_info;
struct ac_surf_info;
struct radeon_surf;
-#define FREE(x) free(x)
-
enum radeon_bo_domain { /* bitfield */
RADEON_DOMAIN_GTT = 2,
RADEON_DOMAIN_VRAM = 4,
#include "radv_cs.h"
#include "sid.h"
#include "radv_util.h"
-#include "main/macros.h"
static void
si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
#include <unistd.h>
#include "util/u_atomic.h"
+#include "util/u_memory.h"
+#include "util/u_math.h"
#define AMDGPU_TILING_SCANOUT_SHIFT 63
#define AMDGPU_TILING_SCANOUT_MASK 1
if (!(bo_flags & RADEON_FLAG_READ_ONLY))
flags |= AMDGPU_VM_PAGE_WRITEABLE;
- size = ALIGN(size, getpagesize());
+ size = align64(size, getpagesize());
return amdgpu_bo_va_op_raw(ws->dev, bo, offset, size, addr,
flags, ops);
#include <pthread.h>
#include <errno.h>
+#include "util/u_memory.h"
#include "ac_debug.h"
#include "radv_radeon_winsys.h"
#include "radv_amdgpu_cs.h"
*/
#include "radv_null_bo.h"
+#include "util/u_memory.h"
static struct radeon_winsys_bo *
radv_null_winsys_bo_create(struct radeon_winsys *_ws,
*/
#include "radv_null_cs.h"
+#include "util/u_memory.h"
struct radv_null_cs {
struct radeon_cmdbuf base;