intel->gen = intelScreen->gen;
const int devID = intelScreen->deviceID;
- if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID))
- intel->gt = 1;
- else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
- intel->gt = 2;
- else if (IS_HSW_GT3(devID))
- intel->gt = 3;
- else
- intel->gt = 0;
-
- if (IS_HASWELL(devID)) {
- intel->is_haswell = true;
- } else if (IS_BAYTRAIL(devID)) {
- intel->is_baytrail = true;
- intel->gt = 1;
- } else if (IS_G4X(devID)) {
- intel->is_g4x = true;
- } else if (IS_945(devID)) {
- intel->is_945 = true;
- }
+
+ intel->is_945 = IS_945(devID);
intel->has_swizzling = intel->intelScreen->hw_has_swizzling;
void (*annotate_aub)(struct intel_context *intel);
bool (*render_target_supported)(struct intel_context *intel,
struct gl_renderbuffer *rb);
-
- /**
- * Surface state operations (i965+ only)
- * \{
- */
- void (*update_texture_surface)(struct gl_context *ctx,
- unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
- void (*update_null_renderbuffer_surface)(struct brw_context *brw,
- unsigned unit);
- void (*create_constant_surface)(struct brw_context *brw,
- drm_intel_bo *bo,
- uint32_t offset,
- uint32_t size,
- uint32_t *out_offset,
- bool dword_pitch);
- /** \} */
} vtbl;
GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */
* Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
*/
int gen;
- int gt;
- bool is_haswell;
- bool is_baytrail;
- bool is_g4x;
bool is_945;
- bool has_llc;
bool has_swizzling;
- int urb_size;
-
drm_intel_context *hw_ctx;
struct intel_batchbuffer batch;