Fix issue with part of PI being 1'bx

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 3b53b008610f5f9575e66e220b8879e0cb260240..ea33152676f931bbd4dfb7d3aee365591c939d3f 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -947,11 +947,13 @@ void AigerReader::post_process()
                        if (other_wire) {
                                other_wire->port_input = false;
                                other_wire->port_output = false;
-                               if (wire->port_input)
-                                       module->connect(other_wire, SigSpec(wire, i));
-                               else
-                                       module->connect(SigSpec(wire, i), other_wire);
                        }
+                       if (wire->port_input && other_wire)
+                               module->connect(other_wire, SigSpec(wire, i));
+                       else
+                                                                 // Since we skip POs that are connected to Sx,
+                                                                 // re-connect them here
+                               module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
                }
        }
 

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 0b83c34a3b69937e175dea9c91db288189211b20..64b625efed521aa6b18c1358dbebf34e892e6a53 100644 (file)
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -262,3 +262,8 @@ endmodule
 module abc9_test025(input [3:0] i, output [3:0] o);
 abc9_test024_sub a(i[2:1], o[2:1]);
 endmodule
+
+module abc9_test026(output [3:0] o, p);
+assign o = { 1'b1, 1'bx };
+assign p = { 1'b1, 1'bx, 1'b0 };
+endmodule