Various fixes/cleanups in alumacc and maccmap

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index d6ee9e66c0f206bc3c1e57cf90c6462c88aa0738..3fddcef13f05ab8b254462470bfa9632216cb4bd 100644 (file)
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -443,7 +443,6 @@ struct AlumaccWorker
                        n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
                        n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
                        n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
-                       log_cell(n->alu_cell);
 
                        for (auto &it : n->cmp)
                        {

diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index c2dc9aa8ac1fdc1264021dee65cb778bc6c163a8..e17231cb532e49cbddada67a9d6801cb442f5992 100644 (file)
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -208,7 +208,17 @@ struct MaccmapWorker
 
                log_assert(tree_sum_bits.empty());
 
-               return module->Add(NEW_ID, summands.front(), summands.back());
+               RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
+               c->setPort("\\A", summands.front());
+               c->setPort("\\B", summands.back());
+               c->setPort("\\CI", RTLIL::S0);
+               c->setPort("\\BI", RTLIL::S0);
+               c->setPort("\\Y", module->addWire(NEW_ID, width));
+               c->setPort("\\X", module->addWire(NEW_ID, width));
+               c->setPort("\\CO", module->addWire(NEW_ID, width));
+               c->fixup_parameters();
+
+               return c->getPort("\\Y");
        }
 };