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power_enums: enable Rc-aware dsld/dsrd
authorDmitry Selyutin <ghostmansd@gmail.com>
Tue, 24 Jan 2023 18:47:09 +0000 (21:47 +0300)
committerDmitry Selyutin <ghostmansd@gmail.com>
Tue, 24 Jan 2023 18:47:09 +0000 (21:47 +0300)
src/openpower/decoder/power_enums.py patch | blob | history

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index e18bceb03c76fe5856327dc9604b3121a41508bb..b7f0278381811137dfc9a88472e60cb0efc9e8ef 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -711,7 +711,7 @@ _insns = [
     "divmod2du",
     "divw", "divwe", "divweo",
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
-    "dsld", "dsrd",
+    "dsld", "dsld.", "dsrd", "dsrd.",
     "eieio", "eqv",
     "extsb", "extsh", "extsw", "extswsli",
     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub