targets/ulx3s: revert to cl=2

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 4a80ee6fb09c1a000152e9d833bb411a3ee7face..f1e21ba73874e0f7f454bb4b4a0398df5782e240 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -63,7 +63,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,