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whoops. mode-bits need to be put in MSB0 order. sigh
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 20:47:02 +0000 (21:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 20:47:02 +0000 (21:47 +0100)
src/openpower/sv/trans/svp64.py patch | blob | history

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index c617375ad8a07148db0c30878077c42070b1ea13..b69448555a0fceabb2668f9b2bf81331cf1655ca 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1349,8 +1349,11 @@ class SVP64Asm:
                     mode |= (predresult << SVP64MODE.BO_LSB)  # set BO
 
         # whewww.... modes all done :)
-        # now put into svp64_rm
-        mode |= sv_mode
+        # now put into svp64_rm, but respect MSB0 order
+        if sv_mode&1:
+            mode |= (0b1<<SVP64MODE.MOD2_LSB)
+        if sv_mode&2:
+            mode |= (0b1<<SVP64MODE.MOD2_MSB)
         # mode: bits 19-23
         svp64_rm.mode = mode