add category descriptions

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 2241be0155aaef562d007e791f320b5c023b6158..c823fb9a058df889d900e3902bbc97fe6b39e333 100644 (file)
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -4,7 +4,8 @@ Based on information from Michael Clark's riscv-meta opcodes table, this
 page categorises and identifies the type of parallelism that SimpleV
 indirectly adds on each RISC-V **standard** opcode.
 
-* **-** no action
+* **-** no change of behaviour takes place: operation remains
+  **completely scalar** even if it has registers.
 * **sv** - a standard contiguous (optionally predicated, optionally
   indirected) multi-register operation where the predication for
   the operation is taken from the **destination** register