II. Files
=========
- sc_slave_port.{cc,hh} -- Implements SCSlavePort
- sc_master_port.{cc,hh} -- Implements SCMasterPort
- sc_mm.{cc,hh} -- Implementation of a TLM memory manager
- sc_ext.{cc,hh} -- TLM extension that carries a gem5 packet
- sc_peq.{cc,hh} -- TLM PEQ for scheduling gem5 events
- sim_control.{cc,hh} -- Implements Gem5SimControl
- slave_transactor.{cc,hh} -- Implements Gem5SlaveTransactor
- master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
-
- example/common/cli_parser.{cc,hh} -- Simple cli argument parser
- example/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
-
- example/slave_port/main.cc -- demonstration of the slave port
- example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
- example/slave_port/tlm.py -- simple gem5 configuration
- example/slave_port/tlm_elastic.py -- gem5 configuration with an elastic
- trace replayer
- example/slave_port/tgen.cfg -- elastic traceplayer configuration
-
- example/master_port/main.cc -- demonstration of the master port
- example/master_port/traffic_generator.{cc/hh}
+ src/sc_slave_port.{cc,hh} -- Implements SCSlavePort
+ src/sc_master_port.{cc,hh} -- Implements SCMasterPort
+ src/sc_mm.{cc,hh} -- Implementation of a TLM memory manager
+ src/sc_ext.{cc,hh} -- TLM extension that carries a gem5 packet
+ src/sc_peq.{cc,hh} -- TLM PEQ for scheduling gem5 events
+ src/sim_control.{cc,hh} -- Implements Gem5SimControl
+ src/slave_transactor.{cc,hh} -- Implements Gem5SlaveTransactor
+ src/master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
+
+ examples/common/cli_parser.{cc,hh} -- Simple cli argument parser
+ examples/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
+
+ examples/slave_port/main.cc -- demonstration of the slave port
+ examples/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
+
+ examples/master_port/main.cc -- demonstration of the master port
+ examples/master_port/traffic_generator.{cc/hh}
-- an example traffic generator module
- example/master_port/tlm.py -- simple gem5 configuration
+
+ conf/tlm_slave.py -- simple gem5 configuration connecting to a
+ SytemC/TLM slave module
+ conf/tlm_elastic_slave.py -- gem5 configuration with an elastic trace
+ replayer
+ conf/tlm_master.py -- simple gem5 configuration connecting to a
+ SytemC/TLM master module
+ conf/tgen.cfg -- trace generator configuration
Other Files will be used from utils/systemc example:
> scons --with-cxx-config --without-python --without-tcmalloc \
> build/ARM/libgem5_opt.dylib
-Set a proper LD_LIBRARY_PATH e.g. for bash:
-> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
-
-or for MAC / OSX:
-> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
-
-The build system finds your SystemC installation using pkg-config. Make sure
-that pkg-config is installed and your systemc.pc is within your
-PKG_CONFIG_PATH. You can add SystemC to the PKG_CONFIG_PATH using the following
-command:
-> export PKG_CONFIG_PATH="/path/to/systemc/lib-<arch>/pkgconfig/:$PKG_CONFIG_PATH"
-
-To build one of the examples:
+To build all sources of the SystemC binding and the examples simply run scons:
-> cd examples/{master,slave}_port
> scons
-> cd ../../
IV. Simple Examples
===================
-> cd examples/{master,slave}_port
-
In order to run our example simulation, we first need to create a config.ini
that represents the gem5 configuration. We do so by starting gem5 with the
desired python configuration script.
-> ../../../../build/ARM/gem5.opt ./tlm.py
+> ../../build/ARM/gem5.opt conf/tlm_{master,slave}.py
The message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
The configuration will be stored in the m5out/ directory
-The build step creates a binary gem5.opt.sc in the example directory. It can
-now be used to load in the generated configuration file from the previous
-normal gem5 run.
+The build step creates a binary 'gem5.sc' for each example in the
+build/examples/{master|slave}_port directories. It can now be used to load in
+the generated configuration file from the previous normal gem5 run.
Try:
-> ./gem5.opt.sc m5out/config.ini -e 1000000
+> build/examples/{master,slave}_port/gem5.sc m5out/config.ini -e 1000000
It should run a simulation for 1us.
To see more information what happens inside the TLM modules use the -v flag:
-> ./gem5.opt.sc m5out/config.ini -e 1000000 -v
-
-To see more information about the port coupling use:
-
-> ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
+> build/{master,slave}_port/gem5.sc m5out/config.ini -e 1000000 -v
V. Full System Setup
Apart from the simple examples, there is a full system example that uses
the gem5-to-TLM bridge.
->cd examples/slave_port
-
Build gem5 as described in Section III. Then, make a config file for the
C++-configured gem5 using normal gem5
-> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
- --tlm-memory=transactor --cpu-type=timing --num-cpu=1 \
+> ../../build/ARM/gem5.opt ../../configs/example/fs.py \
+ --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \
--mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
--l2cache --machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
The message "fatal: Can't find port handler type 'tlm_slave'" is okay.
The configuration will be stored in the m5out/ directory
-The binary 'gem5.opt.sc' can now be used to load in the generated config
-file from the previous normal gem5 run.
+The binary 'build/examples/slave_port/gem5.sc' can now be used to load in the
+generated config file from the previous normal gem5 run.
Try:
-> ./gem5.opt.sc m5out/config.ini -o 2147483648
+> build/examples/slave_port/gem5.sc m5out/config.ini -o 2147483648
The parameter -o specifies the begining of the memory region (0x80000000).
The system should boot now.
-For convenience a run_gem5.sh file holds all those commands
+For convenience a run_gem5_fs.sh file holds all those commands
VI. Elastic Trace Setup
IEEE International Conference on Embedded Computer Systems Architectures
Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
-Similar IV. the simulation can be set up with this command:
+Similar to IV. the simulation can be set up with this command:
-> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
+> ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave.py
Then:
-> ./gem5.opt.sc m5out/config.ini
+> build/examples/slave_port/gem5.sc m5out/config.ini
VII. Knwon issues
* For some toolchains, compiling libgem5 with tcmalloc leads to errors
('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
SystemC application.
-* When SystemC was build with --enable-pthreads, SystemC applications linked
+* When SystemC is build with pthread support enabled, the binding of gem5 to
+ SystemC breaks. When gem5 is linked to a SystemC application, gem5's usage
+ of thread local storage results in a segfault.
--- /dev/null
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+import os
+import sys
+
+
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+#gem5_variant = 'debug'
+
+gem5_root = Dir('#../..').srcnode().abspath
+
+env = Environment()
+
+#Make the gem5 root available in SConscripts
+env['GEM5_ROOT'] = gem5_root
+
+shlibsuffix = env['SHLIBSUFFIX']
+
+# add include dirs
+env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
+ gem5_root + '/util/systemc',
+ gem5_root + '/ext/systemc/src',
+ '#src',
+ '#examples/common',
+ ])
+
+env.Append(CXXFLAGS=['-std=c++11',
+ '-DSC_INCLUDE_DYNAMIC_PROCESSES',
+ '-DTRACING_ON',
+ ])
+
+if gem5_variant == 'debug':
+ env.Append(CXXFLAGS=['-g', '-DDEBUG'])
+
+deps = [] # keep track of all dependencies required for building the binaries
+
+deps += SConscript('src/SConscript', variant_dir='build/tlm', exports='env')
+
+deps += SConscript('examples/common/SConscript',
+ variant_dir='build/examples/common',
+ exports=['env'])
+
+# the SystemC SConscript makes certain assumptions, we need to fulfill these
+# assumptions before calling the SConscript.
+main = env
+sys.path.append(gem5_root + '/src/python')
+AddOption('--no-colors', dest='use_colors', action='store_false',
+ help="Don't add color to abbreviated scons output")
+
+SConscript(gem5_root + '/ext/systemc/SConscript',
+ variant_dir='build/systemc',
+ exports='main')
+
+# By adding libraries as dependencies instead of using LIBS, we avoid that
+# the user needs to set the LD_LIBRARY_PATH
+deps.append(File('build/systemc/libsystemc' + shlibsuffix))
+deps.append(File(os.path.join(gem5_root, 'build', gem5_arch,
+ 'libgem5_' + gem5_variant + shlibsuffix)))
+
+ex_master = SConscript('examples/master_port/SConscript',
+ variant_dir='build/examples/master_port',
+ exports=['env', 'deps'])
+
+ex_slave = SConscript('examples/slave_port/SConscript',
+ variant_dir='build/examples/slave_port',
+ exports=['env', 'deps'])
+
+Default(ex_master + ex_slave)
--- /dev/null
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+
+# This format supports comments using the '#' symbol as the leading
+# character of the line
+#
+# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
+# where the states are the nodes in the graph, init describes what
+# state to start in, and transition describes the edges of the graph.
+#
+# STATE <id> <duration (ticks)> <type>
+#
+# State IDLE idles
+#
+# States LINEAR and RANDOM have additional <percent reads> <start addr>
+# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
+# <data limit (bytes)>
+#
+# State TRACE plays back a pre-recorded trace once
+#
+# Addresses are expressed as decimal numbers. The period in the linear
+# and random state is from a uniform random distribution over the
+# interval. If a specific value is desired, then the min and max can
+# be set to the same value.
+STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64
+INIT 0
+TRANSITION 0 0 1
--- /dev/null
+# Copyright (c) 2016, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+import optparse
+
+from m5.objects import *
+from m5.util import addToPath, fatal
+
+addToPath('../../../configs/common/')
+
+from Caches import *
+
+# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
+# and an external TLM port for SystemC co-simulation.
+#
+# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
+#
+# Base System Architecture:
+#
+# +-----------+ ^
+# +-------------+ | eTraceCPU | |
+# | System Port | +-----+-----+ |
+# +------+------+ | $D1 | $I1 | |
+# | +--+--+--+--+ |
+# | | | | gem5 World
+# | | | | (see this file)
+# | | | |
+# +------v------------v-----v--+ |
+# | Membus | v
+# +----------------+-----------+ External Port (see sc_port.*)
+# | ^
+# +---v---+ | TLM World
+# | TLM | | (see sc_target.*)
+# +-------+ v
+#
+#
+# Create a system with a Crossbar and an Elastic Trace Player as CPU:
+
+# Setup System:
+system = System(cpu=TraceCPU(cpu_id=0),
+ mem_mode='timing',
+ mem_ranges = [AddrRange('512MB')],
+ cache_line_size = 64)
+
+# Create a top-level voltage domain:
+system.voltage_domain = VoltageDomain()
+
+# Create a source clock for the system. This is used as the clock period for
+# xbar and memory:
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain:
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
+# is actually used only by the caches connected to the CPU:
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.cpu_voltage_domain)
+
+# Setup CPU and its L1 caches:
+system.cpu.createInterruptController()
+system.cpu.icache = L1_ICache(size="32kB")
+system.cpu.dcache = L1_DCache(size="32kB")
+system.cpu.icache.cpu_side = system.cpu.icache_port
+system.cpu.dcache.cpu_side = system.cpu.dcache_port
+
+# Assign input trace files to the eTraceCPU:
+system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
+system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
+
+# Setting up L1 BUS:
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory() # This must be instantiated, even if not needed
+
+# Create a external TLM port:
+system.tlm = ExternalSlave()
+system.tlm.addr_ranges = [AddrRange('512MB')]
+system.tlm.port_type = "tlm_slave"
+system.tlm.port_data = "transactor"
+
+# Connect everything:
+system.membus = SystemXBar()
+system.system_port = system.membus.slave
+system.cpu.icache.mem_side = system.membus.slave
+system.cpu.dcache.mem_side = system.membus.slave
+system.membus.master = system.tlm.port
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+m5.instantiate()
+m5.simulate() #Simulation time specified later on commandline
--- /dev/null
+#
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+#
+
+import m5
+from m5.objects import *
+
+import os
+
+# Base System Architecture:
+# +-----+ ^
+# | TLM | | TLM World
+# +--+--+ | (see main.cc)
+# | v
+# +----------v-----------+ External Port (see sc_master_port.*)
+# | Membus | ^
+# +----------+-----------+ |
+# | | gem5 World
+# +---v----+ |
+# | Memory | |
+# +--------+ v
+#
+
+# Create a system with a Crossbar and a simple Memory:
+system = System()
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory(range = AddrRange('512MB'))
+system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+ voltage_domain = VoltageDomain(voltage = '1V'))
+
+# Create a external TLM port:
+system.tlm = ExternalMaster()
+system.tlm.port_type = "tlm_master"
+system.tlm.port_data = "transactor"
+
+# Route the connections:
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+system.tlm.port = system.membus.slave
+system.mem_mode = 'timing'
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+m5.instantiate()
+m5.simulate()
--- /dev/null
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+from m5.objects import *
+
+# This configuration shows a simple setup of a TrafficGen (CPU) and an
+# external TLM port for SystemC co-simulation
+#
+# Base System Architecture:
+# +-------------+ +-----+ ^
+# | System Port | | CPU | |
+# +-------+-----+ +--+--+ |
+# | | | gem5 World
+# | +----+ | (see this file)
+# | | |
+# +-------v------v-------+ |
+# | Membus | v
+# +----------------+-----+ External Port (see sc_slave_port.*)
+# | ^
+# +---v---+ | TLM World
+# | TLM | | (see sc_target.*)
+# +-------+ v
+#
+
+# Create a system with a Crossbar and a TrafficGenerator as CPU:
+system = System()
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory() # This must be instanciated, even if not needed
+system.cpu = TrafficGen(config_file = "conf/tgen.cfg")
+system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+ voltage_domain = VoltageDomain(voltage = '1V'))
+
+# Create a external TLM port:
+system.tlm = ExternalSlave()
+system.tlm.addr_ranges = [AddrRange('512MB')]
+system.tlm.port_type = "tlm_slave"
+system.tlm.port_data = "transactor"
+
+# Route the connections:
+system.cpu.port = system.membus.slave
+system.system_port = system.membus.slave
+system.membus.master = system.tlm.port
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+m5.instantiate()
+m5.simulate() #Simulation time specified later on commandline
--- /dev/null
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+Import('env')
+
+env = env.Clone()
+
+objs = []
+objs += env.Object('cli_parser.cc')
+objs += env.Object('report_handler.cc')
+
+Return('objs')
--- /dev/null
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+Import('env')
+Import('deps')
+
+env = env.Clone()
+
+src = [File('main.cc'), File('traffic_generator.cc')]
+
+bin = env.Program('gem5.sc', src + deps)
+
+Return('bin')
+++ /dev/null
-#!python
-
-# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Christian Menard
-
-import os
-
-gem5_arch = 'ARM'
-gem5_variant = 'opt'
-#gem5_variant = 'debug'
-
-gem5_root = '#../../../..'
-
-target = 'gem5.' + gem5_variant + '.sc'
-
-env = Environment()
-
-# Import PKG_CONFIG_PATH from the external environment
-if os.environ.has_key('PKG_CONFIG_PATH'):
- env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
-
-# search for SystemC
-env.ParseConfig('pkg-config --cflags --libs systemc')
-
-# add include dirs
-env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
- gem5_root + '/util/systemc',
- gem5_root + '/util/tlm',
- '../common'])
-
-env.Append(LIBS=['gem5_' + gem5_variant])
-env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
-
-env.Append(CXXFLAGS=['-std=c++11',
- '-DSC_INCLUDE_DYNAMIC_PROCESSES',
- '-DTRACING_ON'])
-
-if gem5_variant == 'debug':
- env.Append(CXXFLAGS=['-g', '-DDEBUG'])
-
-src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
- gem5_root + '/util/systemc/sc_logger.cc',
- gem5_root + '/util/systemc/sc_module.cc',
- gem5_root + '/util/systemc/stats.cc']
-
-src_tlm = Glob(gem5_root + '/util/tlm/*.cc')
-src_main = Glob('*.cc') + Glob('../common/*.cc')
-
-main = env.Program(target, src_systemc + src_tlm + src_main)
+++ /dev/null
-#
-# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Christian Menard
-#
-
-import m5
-from m5.objects import *
-
-import os
-
-# Base System Architecture:
-# +-----+ ^
-# | TLM | | TLM World
-# +--+--+ | (see main.cc)
-# | v
-# +----------v-----------+ External Port (see sc_master_port.*)
-# | Membus | ^
-# +----------+-----------+ |
-# | | gem5 World
-# +---v----+ |
-# | Memory | |
-# +--------+ v
-#
-
-# Create a system with a Crossbar and a simple Memory:
-system = System()
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory(range = AddrRange('512MB'))
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
- voltage_domain = VoltageDomain(voltage = '1V'))
-
-# Create a external TLM port:
-system.tlm = ExternalMaster()
-system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "transactor"
-
-# Route the connections:
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-system.tlm.port = system.membus.slave
-system.mem_mode = 'timing'
-
-# Start the simulation:
-root = Root(full_system = False, system = system)
-m5.instantiate()
-m5.simulate()
--- /dev/null
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+Import('env')
+Import('deps')
+
+env = env.Clone()
+
+src = [File('main.cc'), File('sc_target.cc')]
+
+bin = env.Program('gem5.sc', src + deps)
+
+Return('bin')
+++ /dev/null
-#!python
-
-# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Christian Menard
-
-import os
-
-gem5_arch = 'ARM'
-gem5_variant = 'opt'
-#gem5_variant = 'debug'
-
-gem5_root = '#../../../..'
-
-target = 'gem5.' + gem5_variant + '.sc'
-
-env = Environment()
-
-# Import PKG_CONFIG_PATH from the external environment
-if os.environ.has_key('PKG_CONFIG_PATH'):
- env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
-
-# search for SystemC
-env.ParseConfig('pkg-config --cflags --libs systemc')
-
-# add include dirs
-env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
- gem5_root + '/util/systemc',
- gem5_root + '/util/tlm',
- '../common'])
-
-env.Append(LIBS=['gem5_' + gem5_variant])
-env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
-
-env.Append(CXXFLAGS=['-std=c++11',
- '-DSC_INCLUDE_DYNAMIC_PROCESSES',
- '-DTRACING_ON'])
-
-if gem5_variant == 'debug':
- env.Append(CXXFLAGS=['-g', '-DDEBUG'])
-
-src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
- gem5_root + '/util/systemc/sc_logger.cc',
- gem5_root + '/util/systemc/sc_module.cc',
- gem5_root + '/util/systemc/stats.cc']
-
-src_tlm = Glob(gem5_root + '/util/tlm/*.cc')
-src_main = Glob('*.cc') + Glob('../common/*.cc')
-
-main = env.Program(target, src_systemc + src_tlm + src_main)
+++ /dev/null
-#!/bin/bash
-# Copyright (c) 2015, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-# Color Definition:
-RCol='\e[0m'; # Text Reset
-BGre='\e[1;31m';
-echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
-
-../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
---tlm-memory=transactor \
---cpu-type=timing \
---num-cpu=1 \
---mem-type=SimpleMemory \
---mem-size=512MB \
---mem-channels=1 \
---caches --l2cache \
---machine-type=VExpress_EMM \
---dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
---kernel=vmlinux.aarch32.ll_20131205.0-gem5
-
-echo -e "\n${BGre}Run gem5 ${RCol}\n"
-
-time ./gem5.opt.sc m5out/config.ini -o 2147483648
+++ /dev/null
-# Copyright (c) 2015, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-
-# This format supports comments using the '#' symbol as the leading
-# character of the line
-#
-# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
-# where the states are the nodes in the graph, init describes what
-# state to start in, and transition describes the edges of the graph.
-#
-# STATE <id> <duration (ticks)> <type>
-#
-# State IDLE idles
-#
-# States LINEAR and RANDOM have additional <percent reads> <start addr>
-# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
-# <data limit (bytes)>
-#
-# State TRACE plays back a pre-recorded trace once
-#
-# Addresses are expressed as decimal numbers. The period in the linear
-# and random state is from a uniform random distribution over the
-# interval. If a specific value is desired, then the min and max can
-# be set to the same value.
-STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64
-INIT 0
-TRANSITION 0 0 1
+++ /dev/null
-# Copyright (c) 2015, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-import m5
-from m5.objects import *
-
-# This configuration shows a simple setup of a TrafficGen (CPU) and an
-# external TLM port for SystemC co-simulation
-#
-# Base System Architecture:
-# +-------------+ +-----+ ^
-# | System Port | | CPU | |
-# +-------+-----+ +--+--+ |
-# | | | gem5 World
-# | +----+ | (see this file)
-# | | |
-# +-------v------v-------+ |
-# | Membus | v
-# +----------------+-----+ External Port (see sc_slave_port.*)
-# | ^
-# +---v---+ | TLM World
-# | TLM | | (see sc_target.*)
-# +-------+ v
-#
-
-# Create a system with a Crossbar and a TrafficGenerator as CPU:
-system = System()
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory() # This must be instanciated, even if not needed
-system.cpu = TrafficGen(config_file = "tgen.cfg")
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
- voltage_domain = VoltageDomain(voltage = '1V'))
-
-# Create a external TLM port:
-system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange('512MB')]
-system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "transactor"
-
-# Route the connections:
-system.cpu.port = system.membus.slave
-system.system_port = system.membus.slave
-system.membus.master = system.tlm.port
-
-# Start the simulation:
-root = Root(full_system = False, system = system)
-root.system.mem_mode = 'timing'
-m5.instantiate()
-m5.simulate() #Simulation time specified later on commandline
+++ /dev/null
-# Copyright (c) 2016, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-import m5
-import optparse
-
-from m5.objects import *
-from m5.util import addToPath, fatal
-
-addToPath('../../../../configs/common/')
-
-from Caches import *
-
-# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
-# and an external TLM port for SystemC co-simulation.
-#
-# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
-#
-# Base System Architecture:
-#
-# +-----------+ ^
-# +-------------+ | eTraceCPU | |
-# | System Port | +-----+-----+ |
-# +------+------+ | $D1 | $I1 | |
-# | +--+--+--+--+ |
-# | | | | gem5 World
-# | | | | (see this file)
-# | | | |
-# +------v------------v-----v--+ |
-# | Membus | v
-# +----------------+-----------+ External Port (see sc_port.*)
-# | ^
-# +---v---+ | TLM World
-# | TLM | | (see sc_target.*)
-# +-------+ v
-#
-#
-# Create a system with a Crossbar and an Elastic Trace Player as CPU:
-
-# Setup System:
-system = System(cpu=TraceCPU(cpu_id=0),
- mem_mode='timing',
- mem_ranges = [AddrRange('512MB')],
- cache_line_size = 64)
-
-# Create a top-level voltage domain:
-system.voltage_domain = VoltageDomain()
-
-# Create a source clock for the system. This is used as the clock period for
-# xbar and memory:
-system.clk_domain = SrcClockDomain(clock = '1GHz',
- voltage_domain = system.voltage_domain)
-
-# Create a CPU voltage domain:
-system.cpu_voltage_domain = VoltageDomain()
-
-# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
-# is actually used only by the caches connected to the CPU:
-system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
- voltage_domain = system.cpu_voltage_domain)
-
-# Setup CPU and its L1 caches:
-system.cpu.createInterruptController()
-system.cpu.icache = L1_ICache(size="32kB")
-system.cpu.dcache = L1_DCache(size="32kB")
-system.cpu.icache.cpu_side = system.cpu.icache_port
-system.cpu.dcache.cpu_side = system.cpu.dcache_port
-
-# Assign input trace files to the eTraceCPU:
-system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
-
-# Setting up L1 BUS:
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory() # This must be instantiated, even if not needed
-
-# Create a external TLM port:
-system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange('512MB')]
-system.tlm.port_type = "tlm"
-system.tlm.port_data = "memory"
-
-# Connect everything:
-system.membus = SystemXBar()
-system.system_port = system.membus.slave
-system.cpu.icache.mem_side = system.membus.slave
-system.cpu.dcache.mem_side = system.membus.slave
-system.membus.master = system.tlm.port
-
-# Start the simulation:
-root = Root(full_system = False, system = system)
-root.system.mem_mode = 'timing'
-m5.instantiate()
-m5.simulate() #Simulation time specified later on commandline
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#include "master_transactor.hh"
-#include "sc_master_port.hh"
-#include "sim_control.hh"
-
-namespace Gem5SystemC
-{
-
-Gem5MasterTransactor::Gem5MasterTransactor(sc_core::sc_module_name name,
- const std::string& portName)
- : sc_core::sc_module(name),
- socket(portName.c_str()),
- sim_control("sim_control"),
- portName(portName)
-{
- if (portName.empty()) {
- SC_REPORT_ERROR(name, "No port name specified!\n");
- }
-}
-
-void
-Gem5MasterTransactor::before_end_of_elaboration()
-{
- auto* port = sim_control->getMasterPort(portName);
-
- port->bindToTransactor(this);
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#ifndef __GEM5_MASTER_TRANSACTOR_HH__
-#define __GEM5_MASTER_TRANSACTOR_HH__
-
-#include <tlm_utils/simple_target_socket.h>
-
-#include <systemc>
-#include <tlm>
-
-#include "sc_master_port.hh"
-#include "sim_control_if.hh"
-
-namespace Gem5SystemC
-{
-
-class Gem5MasterTransactor : public sc_core::sc_module
-{
- public:
- // module interface
- tlm_utils::simple_target_socket<SCMasterPort> socket;
- sc_core::sc_port<Gem5SimControlInterface> sim_control;
-
- private:
- std::string portName;
-
- public:
- SC_HAS_PROCESS(Gem5MasterTransactor);
-
- Gem5MasterTransactor(sc_core::sc_module_name name,
- const std::string& portName);
-
- void before_end_of_elaboration();
-};
-
-}
-
-#endif
--- /dev/null
+#!/bin/bash
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+# Color Definition:
+RCol='\e[0m'; # Text Reset
+BGre='\e[1;31m';
+echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
+
+../../build/ARM/gem5.opt ../../configs/example/fs.py \
+--tlm-memory=transactor \
+--cpu-type=TimingSimpleCPU \
+--num-cpu=1 \
+--mem-type=SimpleMemory \
+--mem-size=512MB \
+--mem-channels=1 \
+--caches --l2cache \
+--machine-type=VExpress_EMM \
+--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
+--kernel=vmlinux.aarch32.ll_20131205.0-gem5
+
+echo -e "\n${BGre}Run gem5 ${RCol}\n"
+
+time ./build/examples/slave_port/gem5.sc m5out/config.ini -o 2147483648
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- * Matthias Jung
- * Christian Menard
- */
-
-#include "sc_ext.hh"
-
-using namespace tlm;
-
-namespace Gem5SystemC
-{
-
-Gem5Extension::Gem5Extension(PacketPtr packet)
-{
- Packet = packet;
- pipeThrough = false;
-}
-
-Gem5Extension& Gem5Extension::getExtension(const tlm_generic_payload *payload)
-{
- Gem5Extension *result = NULL;
- payload->get_extension(result);
- sc_assert(result!=NULL);
- return *result;
-}
-
-Gem5Extension& Gem5Extension::getExtension(const tlm_generic_payload &payload)
-{
- return Gem5Extension::getExtension(&payload);
-}
-
-PacketPtr Gem5Extension::getPacket()
-{
- return Packet;
-}
-
-tlm_extension_base* Gem5Extension::clone() const
-{
- return new Gem5Extension(Packet);
-}
-
-void Gem5Extension::copy_from(const tlm_extension_base& ext)
-{
- const Gem5Extension& cpyFrom = static_cast<const Gem5Extension&>(ext);
- Packet = cpyFrom.Packet;
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- * Matthias Jung
- * Christian Menard
- */
-
-#ifndef __SC_EXT_HH__
-#define __SC_EXT_HH__
-
-#include <systemc.h>
-#include <tlm.h>
-
-#include <iostream>
-
-#include "mem/packet.hh"
-
-namespace Gem5SystemC
-{
-
-class Gem5Extension: public tlm::tlm_extension<Gem5Extension>
-{
- public:
- Gem5Extension(PacketPtr packet);
-
- virtual tlm_extension_base* clone() const;
- virtual void copy_from(const tlm_extension_base& ext);
-
- static Gem5Extension&
- getExtension(const tlm::tlm_generic_payload *payload);
- static Gem5Extension&
- getExtension(const tlm::tlm_generic_payload &payload);
- PacketPtr getPacket();
-
- bool isPipeThrough() const { return pipeThrough; }
- void setPipeThrough() { pipeThrough = true; }
-
- private:
- PacketPtr Packet;
- bool pipeThrough;
-};
-
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#include <sstream>
-
-#include "master_transactor.hh"
-#include "params/ExternalMaster.hh"
-#include "sc_ext.hh"
-#include "sc_master_port.hh"
-#include "sim/system.hh"
-
-namespace Gem5SystemC
-{
-
-PacketPtr
-SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans)
-{
- Request::Flags flags;
- auto req = new Request(trans.get_address(), trans.get_data_length(), flags,
- owner.masterId);
-
- MemCmd cmd;
-
- switch (trans.get_command()) {
- case tlm::TLM_READ_COMMAND:
- cmd = MemCmd::ReadReq;
- break;
- case tlm::TLM_WRITE_COMMAND:
- cmd = MemCmd::WriteReq;
- break;
- default:
- SC_REPORT_FATAL("SCMasterPort",
- "received transaction with unsupported command");
- }
-
- /*
- * Allocate a new Packet. The packet will be deleted when it returns from
- * the gem5 world as a response.
- */
- auto pkt = new Packet(req, cmd);
- pkt->dataStatic(trans.get_data_ptr());
-
- return pkt;
-}
-
-void
-SCMasterPort::destroyPacket(PacketPtr pkt)
-{
- delete pkt;
-}
-
-SCMasterPort::SCMasterPort(const std::string& name_,
- const std::string& systemc_name,
- ExternalMaster& owner_,
- Gem5SimControl& simControl)
- : ExternalMaster::Port(name_, owner_),
- peq(this, &SCMasterPort::peq_cb),
- waitForRetry(false),
- pendingRequest(nullptr),
- pendingPacket(nullptr),
- needToSendRetry(false),
- responseInProgress(false),
- transactor(nullptr),
- simControl(simControl)
-{
- system =
- dynamic_cast<const ExternalMasterParams*>(owner_.params())->system;
-}
-
-void
-SCMasterPort::bindToTransactor(Gem5MasterTransactor* transactor)
-{
- sc_assert(this->transactor == nullptr);
-
- this->transactor = transactor;
-
- /*
- * Register the TLM non-blocking interface when using gem5 Timing mode and
- * the TLM blocking interface when using the gem5 Atomic mode.
- * Then the magic (TM) in simple_target_socket automatically transforms
- * non-blocking in blocking transactions and vice versa.
- *
- * NOTE: The mode may change during execution.
- */
- if (system->isTimingMode()) {
- SC_REPORT_INFO("SCMasterPort", "register non-blocking interface");
- transactor->socket.register_nb_transport_fw(this,
- &SCMasterPort::nb_transport_fw);
- } else if (system->isAtomicMode()) {
- SC_REPORT_INFO("SCMasterPort", "register blocking interface");
- transactor->socket.register_b_transport(this,
- &SCMasterPort::b_transport);
- } else {
- panic("gem5 operates neither in Timing nor in Atomic mode");
- }
-
- transactor->socket.register_transport_dbg(this,
- &SCMasterPort::transport_dbg);
-}
-
-void
-SCMasterPort::checkTransaction(tlm::tlm_generic_payload& trans)
-{
- if (trans.is_response_error()) {
- std::stringstream ss;
- ss << "Transaction returned with error, response status = "
- << trans.get_response_string();
- SC_REPORT_ERROR("TLM-2", ss.str().c_str());
- }
-}
-
-tlm::tlm_sync_enum
-SCMasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans,
- tlm::tlm_phase& phase, sc_core::sc_time& delay)
-{
- uint64_t adr = trans.get_address();
- unsigned len = trans.get_data_length();
- unsigned char* byteEnable = trans.get_byte_enable_ptr();
- unsigned width = trans.get_streaming_width();
-
- // check the transaction attributes for unsupported features ...
- if (byteEnable != 0) {
- trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
- return tlm::TLM_COMPLETED;
- }
- if (width < len) { // is this a burst request?
- trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
- return tlm::TLM_COMPLETED;
- }
-
- // ... and queue the valid transaction
- trans.acquire();
- peq.notify(trans, phase, delay);
- return tlm::TLM_ACCEPTED;
-}
-
-void
-SCMasterPort::peq_cb(tlm::tlm_generic_payload& trans,
- const tlm::tlm_phase& phase)
-{
- // catch up with SystemC time
- simControl.catchup();
- assert(curTick() == sc_core::sc_time_stamp().value());
-
- switch (phase) {
- case tlm::BEGIN_REQ:
- handleBeginReq(trans);
- break;
- case tlm::END_RESP:
- handleEndResp(trans);
- break;
- default:
- panic("unimplemented phase in callback");
- }
-
- // the functions called above may have scheduled gem5 events
- // -> notify the event loop handler
- simControl.notify();
-}
-
-void
-SCMasterPort::handleBeginReq(tlm::tlm_generic_payload& trans)
-{
- sc_assert(!waitForRetry);
- sc_assert(pendingRequest == nullptr);
- sc_assert(pendingPacket == nullptr);
-
- trans.acquire();
-
- PacketPtr pkt = nullptr;
-
- Gem5Extension* extension = nullptr;
- trans.get_extension(extension);
-
- // If there is an extension, this transaction was initiated by the gem5
- // world and we can pipe through the original packet. Otherwise, we
- // generate a new packet based on the transaction.
- if (extension != nullptr) {
- extension->setPipeThrough();
- pkt = extension->getPacket();
- } else {
- pkt = generatePacket(trans);
- }
-
- auto tlmSenderState = new TlmSenderState(trans);
- pkt->pushSenderState(tlmSenderState);
-
- if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
- sendEndReq(trans);
- trans.release();
- } else { // port is blocked -> wait for retry before sending END_REQ
- waitForRetry = true;
- pendingRequest = &trans;
- pendingPacket = pkt;
- }
-}
-
-void
-SCMasterPort::handleEndResp(tlm::tlm_generic_payload& trans)
-{
- sc_assert(responseInProgress);
-
- responseInProgress = false;
-
- checkTransaction(trans);
-
- if (needToSendRetry) {
- sendRetryResp();
- needToSendRetry = false;
- }
-}
-
-void
-SCMasterPort::sendEndReq(tlm::tlm_generic_payload& trans)
-{
- tlm::tlm_phase phase = tlm::END_REQ;
- auto delay = sc_core::SC_ZERO_TIME;
-
- auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
- panic_if(status != tlm::TLM_ACCEPTED,
- "Unexpected status after sending END_REQ");
-}
-
-void
-SCMasterPort::b_transport(tlm::tlm_generic_payload& trans,
- sc_core::sc_time& t)
-{
- Gem5Extension* extension = nullptr;
- trans.get_extension(extension);
-
- PacketPtr pkt = nullptr;
-
- // If there is an extension, this transaction was initiated by the gem5
- // world and we can pipe through the original packet.
- if (extension != nullptr) {
- extension->setPipeThrough();
- pkt = extension->getPacket();
- } else {
- pkt = generatePacket(trans);
- }
-
- Tick ticks = sendAtomic(pkt);
-
- // send an atomic request to gem5
- panic_if(pkt->needsResponse() && !pkt->isResponse(),
- "Packet sending failed!\n");
-
- // one tick is a pico second
- auto delay =
- sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
-
- // update time
- t += delay;
-
- if (extension != nullptr)
- destroyPacket(pkt);
-
- trans.set_response_status(tlm::TLM_OK_RESPONSE);
-}
-
-unsigned int
-SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans)
-{
- Gem5Extension* extension = nullptr;
- trans.get_extension(extension);
-
- // If there is an extension, this transaction was initiated by the gem5
- // world and we can pipe through the original packet.
- if (extension != nullptr) {
- extension->setPipeThrough();
- sendFunctional(extension->getPacket());
- } else {
- auto pkt = generatePacket(trans);
- sendFunctional(pkt);
- destroyPacket(pkt);
- }
-
- return trans.get_data_length();
-}
-
-bool
-SCMasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
- tlm::tlm_dmi& dmi_data)
-{
- return false;
-}
-
-bool
-SCMasterPort::recvTimingResp(PacketPtr pkt)
-{
- // exclusion rule
- // We need to Wait for END_RESP before sending next BEGIN_RESP
- if (responseInProgress) {
- sc_assert(!needToSendRetry);
- needToSendRetry = true;
- return false;
- }
-
- sc_assert(pkt->isResponse());
-
- /*
- * Pay for annotated transport delays.
- *
- * See recvTimingReq in sc_slave_port.cc for a detailed description.
- */
- auto delay = sc_core::sc_time::from_value(pkt->payloadDelay);
- // reset the delays
- pkt->payloadDelay = 0;
- pkt->headerDelay = 0;
-
- auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
- sc_assert(tlmSenderState != nullptr);
-
- auto& trans = tlmSenderState->trans;
-
- Gem5Extension* extension = nullptr;
- trans.get_extension(extension);
-
- // clean up
- delete tlmSenderState;
-
- // If there is an extension the packet was piped through and we must not
- // delete it. The packet travels back with the transaction.
- if (extension == nullptr)
- destroyPacket(pkt);
- else
- sc_assert(extension->isPipeThrough());
-
- sendBeginResp(trans, delay);
- trans.release();
-
- return true;
-}
-
-void
-SCMasterPort::sendBeginResp(tlm::tlm_generic_payload& trans,
- sc_core::sc_time& delay)
-{
- tlm::tlm_phase phase = tlm::BEGIN_RESP;
-
- trans.set_response_status(tlm::TLM_OK_RESPONSE);
-
- auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
-
- if (status == tlm::TLM_COMPLETED ||
- status == tlm::TLM_UPDATED && phase == tlm::END_RESP) {
- // transaction completed -> no need to wait for tlm::END_RESP
- responseInProgress = false;
- } else if (status == tlm::TLM_ACCEPTED) {
- // we need to wait for tlm::END_RESP
- responseInProgress = true;
- } else {
- panic("Unexpected status after sending BEGIN_RESP");
- }
-}
-
-void
-SCMasterPort::recvReqRetry()
-{
- sc_assert(waitForRetry);
- sc_assert(pendingRequest != nullptr);
- sc_assert(pendingPacket != nullptr);
-
- if (sendTimingReq(pendingPacket)) {
- waitForRetry = false;
- pendingPacket = nullptr;
-
- auto& trans = *pendingRequest;
- sendEndReq(trans);
- trans.release();
-
- pendingRequest = nullptr;
- }
-}
-
-void
-SCMasterPort::recvRangeChange()
-{
- SC_REPORT_WARNING("SCMasterPort",
- "received address range change but ignored it");
-}
-
-ExternalMaster::Port*
-SCMasterPortHandler::getExternalPort(const std::string &name,
- ExternalMaster &owner,
- const std::string &port_data)
-{
- // Create and register a new SystemC master port
- auto* port = new SCMasterPort(name, port_data, owner, control);
-
- control.registerMasterPort(port_data, port);
-
- return port;
-}
-
-} // namespace Gem5SystemC
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#ifndef __SC_MASTER_PORT_HH__
-#define __SC_MASTER_PORT_HH__
-
-#include <tlm_utils/peq_with_cb_and_phase.h>
-
-#include <systemc>
-#include <tlm>
-
-#include <mem/external_master.hh>
-#include <sc_peq.hh>
-#include <sim_control.hh>
-
-namespace Gem5SystemC
-{
-
-// forward declaration
-class Gem5MasterTransactor;
-
-/**
- * This is a gem5 master port that translates TLM transactions to gem5 packets.
- *
- * Upon receiving a TLM transaction (b_transport, nb_transport_fw,
- * dbg_transport) the port generates a gem5 packet and initializes the packet
- * with information from the transaction payload. The original TLM payload is
- * added as a sender state to the gem5 packet. This way the payload can be
- * restored when the response packet arrives at the port.
- *
- * Special care is required, when the TLM transaction originates from a
- * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
- * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
- * interconnect. In this case, the master port restores the original packet
- * from the payload extension (added by the SCSlavePort) and forwards it to the
- * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
- *
- * If gem5 operates in atomic mode, the master port registers the TLM blocking
- * interface and automatically translates non-blocking requests to blocking.
- * If gem5 operates in timing mode, the transactor registers the non-blocking
- * interface. Then, the transactor automatically translated blocking requests.
- * It is assumed that the mode (atomic/timing) does not change during
- * execution.
- */
-class SCMasterPort : public ExternalMaster::Port
-{
- private:
- struct TlmSenderState : public Packet::SenderState
- {
- tlm::tlm_generic_payload& trans;
- TlmSenderState(tlm::tlm_generic_payload& trans)
- : trans(trans)
- {
- }
- };
-
- tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
-
- bool waitForRetry;
- tlm::tlm_generic_payload* pendingRequest;
- PacketPtr pendingPacket;
-
- bool needToSendRetry;
-
- bool responseInProgress;
-
- Gem5MasterTransactor* transactor;
-
- System* system;
-
- Gem5SimControl& simControl;
-
- protected:
- // payload event call back
- void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
-
- // The TLM target interface
- tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
- tlm::tlm_phase& phase,
- sc_core::sc_time& t);
- void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
- unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
- bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
- tlm::tlm_dmi& dmi_data);
-
- // Gem5 SCMasterPort interface
- bool recvTimingResp(PacketPtr pkt);
- void recvReqRetry();
- void recvRangeChange();
-
- public:
- SCMasterPort(const std::string& name_,
- const std::string& systemc_name,
- ExternalMaster& owner_,
- Gem5SimControl& simControl);
-
- void bindToTransactor(Gem5MasterTransactor* transactor);
-
- friend PayloadEvent<SCMasterPort>;
-
- private:
- void sendEndReq(tlm::tlm_generic_payload& trans);
- void sendBeginResp(tlm::tlm_generic_payload& trans,
- sc_core::sc_time& delay);
-
- void handleBeginReq(tlm::tlm_generic_payload& trans);
- void handleEndResp(tlm::tlm_generic_payload& trans);
-
- PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
- void destroyPacket(PacketPtr pkt);
-
- void checkTransaction(tlm::tlm_generic_payload& trans);
-};
-
-class SCMasterPortHandler : public ExternalMaster::Handler
-{
- private:
- Gem5SimControl& control;
-
- public:
- SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
-
- ExternalMaster::Port *getExternalPort(const std::string &name,
- ExternalMaster &owner,
- const std::string &port_data);
-};
-
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- * Robert Gernhardt
- * Matthias Jung
- */
-
-#include <iostream>
-
-#include "sc_mm.hh"
-
-using namespace std;
-
-namespace Gem5SystemC
-{
-
-MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0)
-{
-
-}
-
-MemoryManager::~MemoryManager()
-{
- for (gp* payload: freePayloads) {
- delete payload;
- numberOfFrees++;
- }
-}
-
-gp*
-MemoryManager::allocate()
-{
- if (freePayloads.empty()) {
- numberOfAllocations++;
- return new gp(this);
- } else {
- gp* result = freePayloads.back();
- freePayloads.pop_back();
- return result;
- }
-}
-
-void
-MemoryManager::free(gp* payload)
-{
- payload->reset(); //clears all extensions
- freePayloads.push_back(payload);
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- * Robert Gernhardt
- * Matthias Jung
- */
-
-#ifndef __SC_MM_HH__
-#define __SC_MM_HH__
-
-#include <tlm.h>
-
-#include <vector>
-
-namespace Gem5SystemC
-{
-
-typedef tlm::tlm_generic_payload gp;
-
-class MemoryManager : public tlm::tlm_mm_interface
-{
- public:
- MemoryManager();
- virtual ~MemoryManager();
- virtual gp* allocate();
- virtual void free(gp* payload);
-
- private:
- unsigned int numberOfAllocations;
- unsigned int numberOfFrees;
- std::vector<gp*> freePayloads;
-};
-
-}
-
-#endif /* __SC_MM_HH__ */
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Matthias Jung
- * Christian Menard
- */
-
-#ifndef PAYLOAD_EVENT_H_
-#define PAYLOAD_EVENT_H_
-
-// TLM includes
-#include <tlm.h>
-
-// gem5 includes
-#include <sim/eventq.hh>
-
-namespace Gem5SystemC {
-/**
- * A 'Fake Payload Event Queue', similar to the TLM PEQs. This helps the
- * transactors to schedule events in gem5.
- */
-template <typename OWNER>
-class PayloadEvent : public Event
-{
- public:
- OWNER& port;
- const std::string eventName;
- void (OWNER::*handler)(PayloadEvent<OWNER>* pe,
- tlm::tlm_generic_payload& trans,
- const tlm::tlm_phase& phase);
-
- protected:
- tlm::tlm_generic_payload* t;
- tlm::tlm_phase p;
-
- void process() { (port.*handler)(this, *t, p); }
-
- public:
- const std::string name() const { return eventName; }
-
- PayloadEvent(OWNER& port_,
- void (OWNER::*handler_)(PayloadEvent<OWNER>* pe,
- tlm::tlm_generic_payload& trans,
- const tlm::tlm_phase& phase),
- const std::string& event_name)
- : port(port_)
- , eventName(event_name)
- , handler(handler_)
- {
- }
-
- /// Schedule an event into gem5
- void notify(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase,
- const sc_core::sc_time& delay)
- {
- assert(!scheduled());
-
- t = &trans;
- p = phase;
-
- /**
- * Get time from SystemC as this will always be more up to date
- * than gem5's
- */
- Tick nextEventTick = sc_core::sc_time_stamp().value() + delay.value();
-
- port.owner.wakeupEventQueue(nextEventTick);
- port.owner.schedule(this, nextEventTick);
- }
-};
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Matthias Jung
- * Abdul Mutaal Ahmad
- * Christian Menard
- */
-
-#include "sc_ext.hh"
-#include "sc_mm.hh"
-#include "sc_slave_port.hh"
-#include "slave_transactor.hh"
-
-namespace Gem5SystemC
-{
-
-/**
- * Instantiate a tlm memory manager that takes care about all the
- * tlm transactions in the system
- */
-MemoryManager mm;
-
-/**
- * Convert a gem5 packet to a TLM payload by copying all the relevant
- * information to a previously allocated tlm payload
- */
-void
-packet2payload(PacketPtr packet, tlm::tlm_generic_payload &trans)
-{
- trans.set_address(packet->getAddr());
-
- /* Check if this transaction was allocated by mm */
- sc_assert(trans.has_mm());
-
- unsigned int size = packet->getSize();
- unsigned char *data = packet->getPtr<unsigned char>();
-
- trans.set_data_length(size);
- trans.set_streaming_width(size);
- trans.set_data_ptr(data);
-
- if (packet->isRead()) {
- trans.set_command(tlm::TLM_READ_COMMAND);
- }
- else if (packet->isInvalidate()) {
- /* Do nothing */
- } else if (packet->isWrite()) {
- trans.set_command(tlm::TLM_WRITE_COMMAND);
- } else {
- SC_REPORT_FATAL("SCSlavePort", "No R/W packet");
- }
-}
-
-/**
- * Similar to TLM's blocking transport (LT)
- */
-Tick
-SCSlavePort::recvAtomic(PacketPtr packet)
-{
- CAUGHT_UP;
- SC_REPORT_INFO("SCSlavePort", "recvAtomic hasn't been tested much");
-
- panic_if(packet->cacheResponding(), "Should not see packets where cache "
- "is responding");
-
- panic_if(!(packet->isRead() || packet->isWrite()),
- "Should only see read and writes at TLM memory\n");
-
-
- sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
-
-
- /* Prepare the transaction */
- tlm::tlm_generic_payload * trans = mm.allocate();
- trans->acquire();
- packet2payload(packet, *trans);
-
- /* Attach the packet pointer to the TLM transaction to keep track */
- Gem5Extension* extension = new Gem5Extension(packet);
- trans->set_auto_extension(extension);
-
- /* Execute b_transport: */
- if (packet->cmd == MemCmd::SwapReq) {
- SC_REPORT_FATAL("SCSlavePort", "SwapReq not supported");
- } else if (packet->isRead()) {
- transactor->socket->b_transport(*trans, delay);
- } else if (packet->isInvalidate()) {
- // do nothing
- } else if (packet->isWrite()) {
- transactor->socket->b_transport(*trans, delay);
- } else {
- SC_REPORT_FATAL("SCSlavePort", "Typo of request not supported");
- }
-
- if (packet->needsResponse()) {
- packet->makeResponse();
- }
-
- trans->release();
-
- return delay.value();
-}
-
-/**
- * Similar to TLM's debug transport
- */
-void
-SCSlavePort::recvFunctional(PacketPtr packet)
-{
- /* Prepare the transaction */
- tlm::tlm_generic_payload * trans = mm.allocate();
- trans->acquire();
- packet2payload(packet, *trans);
-
- /* Attach the packet pointer to the TLM transaction to keep track */
- Gem5Extension* extension = new Gem5Extension(packet);
- trans->set_auto_extension(extension);
-
- /* Execute Debug Transport: */
- unsigned int bytes = transactor->socket->transport_dbg(*trans);
- if (bytes != trans->get_data_length()) {
- SC_REPORT_FATAL("SCSlavePort","debug transport was not completed");
- }
-
- trans->release();
-}
-
-bool
-SCSlavePort::recvTimingSnoopResp(PacketPtr packet)
-{
- /* Snooping should be implemented with tlm_dbg_transport */
- SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvTimingSnoopResp");
- return false;
-}
-
-void
-SCSlavePort::recvFunctionalSnoop(PacketPtr packet)
-{
- /* Snooping should be implemented with tlm_dbg_transport */
- SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvFunctionalSnoop");
-}
-
-/**
- * Similar to TLM's non-blocking transport (AT)
- */
-bool
-SCSlavePort::recvTimingReq(PacketPtr packet)
-{
- CAUGHT_UP;
-
- panic_if(packet->cacheResponding(), "Should not see packets where cache "
- "is responding");
-
- panic_if(!(packet->isRead() || packet->isWrite()),
- "Should only see read and writes at TLM memory\n");
-
-
- /* We should never get a second request after noting that a retry is
- * required */
- sc_assert(!needToSendRequestRetry);
-
- /* Remember if a request comes in while we're blocked so that a retry
- * can be sent to gem5 */
- if (blockingRequest) {
- needToSendRequestRetry = true;
- return false;
- }
-
- /* NOTE: normal tlm is blocking here. But in our case we return false
- * and tell gem5 when a retry can be done. This is the main difference
- * in the protocol:
- * if (requestInProgress)
- * {
- * wait(endRequestEvent);
- * }
- * requestInProgress = trans;
- */
-
- /* Prepare the transaction */
- tlm::tlm_generic_payload * trans = mm.allocate();
- trans->acquire();
- packet2payload(packet, *trans);
-
- /* Attach the packet pointer to the TLM transaction to keep track */
- Gem5Extension* extension = new Gem5Extension(packet);
- trans->set_auto_extension(extension);
-
- /*
- * Pay for annotated transport delays.
- *
- * The header delay marks the point in time, when the packet first is seen
- * by the transactor. This is the point int time, when the transactor needs
- * to send the BEGIN_REQ to the SystemC world.
- *
- * NOTE: We drop the payload delay here. Normally, the receiver would be
- * responsible for handling the payload delay. In this case, however,
- * the receiver is a SystemC module and has no notion of the gem5
- * transport protocol and we cannot simply forward the
- * payload delay to the receiving module. Instead, we expect the
- * receiving SystemC module to model the payload delay by deferring
- * the END_REQ. This could lead to incorrect delays, if the XBar
- * payload delay is longer than the time the receiver needs to accept
- * the request (time between BEGIN_REQ and END_REQ).
- *
- * TODO: We could detect the case described above by remembering the
- * payload delay and comparing it to the time between BEGIN_REQ and
- * END_REQ. Then, a warning should be printed.
- */
- auto delay = sc_core::sc_time::from_value(packet->payloadDelay);
- // reset the delays
- packet->payloadDelay = 0;
- packet->headerDelay = 0;
-
- /* Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
- * Standard Page 507 for a visualisation of the procedure */
- tlm::tlm_phase phase = tlm::BEGIN_REQ;
- tlm::tlm_sync_enum status;
- status = transactor->socket->nb_transport_fw(*trans, phase, delay);
- /* Check returned value: */
- if (status == tlm::TLM_ACCEPTED) {
- sc_assert(phase == tlm::BEGIN_REQ);
- /* Accepted but is now blocking until END_REQ (exclusion rule)*/
- blockingRequest = trans;
- } else if (status == tlm::TLM_UPDATED) {
- /* The Timing annotation must be honored: */
- sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
-
- PayloadEvent<SCSlavePort> * pe;
- pe = new PayloadEvent<SCSlavePort>(*this,
- &SCSlavePort::pec, "PEQ");
- pe->notify(*trans, phase, delay);
- } else if (status == tlm::TLM_COMPLETED) {
- /* Transaction is over nothing has do be done. */
- sc_assert(phase == tlm::END_RESP);
- trans->release();
- }
-
- return true;
-}
-
-void
-SCSlavePort::pec(
- PayloadEvent<SCSlavePort> * pe,
- tlm::tlm_generic_payload& trans,
- const tlm::tlm_phase& phase)
-{
- sc_time delay;
-
- if (phase == tlm::END_REQ ||
- &trans == blockingRequest && phase == tlm::BEGIN_RESP) {
- sc_assert(&trans == blockingRequest);
- blockingRequest = NULL;
-
- /* Did another request arrive while blocked, schedule a retry */
- if (needToSendRequestRetry) {
- needToSendRequestRetry = false;
- sendRetryReq();
- }
- }
- if (phase == tlm::BEGIN_RESP)
- {
- CAUGHT_UP;
-
- auto& extension = Gem5Extension::getExtension(trans);
- auto packet = extension.getPacket();
-
- sc_assert(!blockingResponse);
-
- bool need_retry = false;
-
- /*
- * If the packet was piped through and needs a response, we don't need
- * to touch the packet and can forward it directly as a response.
- * Otherwise, we need to make a response and send the transformed
- * packet.
- */
- if (extension.isPipeThrough()) {
- if (packet->isResponse()) {
- need_retry = !sendTimingResp(packet);
- }
- } else if (packet->needsResponse()) {
- packet->makeResponse();
- need_retry = !sendTimingResp(packet);
- }
-
- if (need_retry) {
- blockingResponse = &trans;
- } else {
- if (phase == tlm::BEGIN_RESP) {
- /* Send END_RESP and we're finished: */
- tlm::tlm_phase fw_phase = tlm::END_RESP;
- sc_time delay = SC_ZERO_TIME;
- transactor->socket->nb_transport_fw(trans, fw_phase, delay);
- /* Release the transaction with all the extensions */
- trans.release();
- }
- }
- }
- delete pe;
-}
-
-void
-SCSlavePort::recvRespRetry()
-{
- CAUGHT_UP;
-
- /* Retry a response */
- sc_assert(blockingResponse);
-
- tlm::tlm_generic_payload *trans = blockingResponse;
- blockingResponse = NULL;
- PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();
-
- bool need_retry = !sendTimingResp(packet);
-
- sc_assert(!need_retry);
-
- sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
- tlm::tlm_phase phase = tlm::END_RESP;
- transactor->socket->nb_transport_fw(*trans, phase, delay);
- // Release transaction with all the extensions
- trans->release();
-}
-
-tlm::tlm_sync_enum
-SCSlavePort::nb_transport_bw(tlm::tlm_generic_payload& trans,
- tlm::tlm_phase& phase,
- sc_core::sc_time& delay)
-{
- PayloadEvent<SCSlavePort> * pe;
- pe = new PayloadEvent<SCSlavePort>(*this, &SCSlavePort::pec, "PE");
- pe->notify(trans, phase, delay);
- return tlm::TLM_ACCEPTED;
-}
-
-SCSlavePort::SCSlavePort(const std::string &name_,
- const std::string &systemc_name,
- ExternalSlave &owner_) :
- ExternalSlave::Port(name_, owner_),
- blockingRequest(NULL),
- needToSendRequestRetry(false),
- blockingResponse(NULL),
- transactor(nullptr)
-{
-}
-
-void
-SCSlavePort::bindToTransactor(Gem5SlaveTransactor* transactor)
-{
- sc_assert(this->transactor == nullptr);
-
- this->transactor = transactor;
-
- transactor->socket.register_nb_transport_bw(this,
- &SCSlavePort::nb_transport_bw);
-}
-
-ExternalSlave::Port*
-SCSlavePortHandler::getExternalPort(const std::string &name,
- ExternalSlave &owner,
- const std::string &port_data)
-{
- // Create and register a new SystemC slave port
- auto* port = new SCSlavePort(name, port_data, owner);
-
- control.registerSlavePort(port_data, port);
-
- return port;
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Matthias Jung
- * Christian Menard
- */
-
-#ifndef __SC_SLAVE_PORT_HH__
-#define __SC_SLAVE_PORT_HH__
-
-#include <systemc>
-#include <tlm>
-
-#include "mem/external_slave.hh"
-#include "sc_mm.hh"
-#include "sc_peq.hh"
-#include "sim_control.hh"
-
-namespace Gem5SystemC
-{
-
-// forward declaration
-class Gem5SlaveTransactor;
-
-/**
- * Test that gem5 is at the same time as SystemC
- */
-#define CAUGHT_UP do { \
- assert(curTick() == sc_core::sc_time_stamp().value()); \
-} while (0)
-
-/**
- * This is a gem5 slave port that translates gem5 packets to TLM transactions.
- *
- * Upon receiving a packet (recvAtomic, recvTiningReq, recvFunctional) the port
- * creates a new TLM payload and initializes it with information from the gem5
- * packet. The original packet is added as an extension to the TLM payload.
- * Then the port issues a TLM transaction in the SystemC world. By storing the
- * original packet as a payload extension, the packet can be restored and send
- * back to the gem5 world upon receiving a response from the SystemC world.
- */
-class SCSlavePort : public ExternalSlave::Port
-{
- public:
- /** One instance of pe and the related callback needed */
- //payloadEvent<SCSlavePort> pe;
- void pec(PayloadEvent<SCSlavePort> * pe,
- tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
-
- /**
- * A transaction after BEGIN_REQ has been sent but before END_REQ, which
- * is blocking the request channel (Exlusion Rule, see IEEE1666)
- */
- tlm::tlm_generic_payload *blockingRequest;
-
- /**
- * Did another gem5 request arrive while currently blocked?
- * This variable is needed when a retry should happen
- */
- bool needToSendRequestRetry;
-
- /**
- * A response which has been asked to retry by gem5 and so is blocking
- * the response channel
- */
- tlm::tlm_generic_payload *blockingResponse;
-
- protected:
- /** The gem5 Port slave interface */
- Tick recvAtomic(PacketPtr packet);
- void recvFunctional(PacketPtr packet);
- bool recvTimingReq(PacketPtr packet);
- bool recvTimingSnoopResp(PacketPtr packet);
- void recvRespRetry();
- void recvFunctionalSnoop(PacketPtr packet);
-
- Gem5SlaveTransactor* transactor;
-
- public:
- /** The TLM initiator interface */
- tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
- tlm::tlm_phase& phase,
- sc_core::sc_time& t);
-
- SCSlavePort(const std::string &name_,
- const std::string &systemc_name,
- ExternalSlave &owner_);
-
- void bindToTransactor(Gem5SlaveTransactor* transactor);
-
- friend PayloadEvent<SCSlavePort>;
-};
-
-class SCSlavePortHandler : public ExternalSlave::Handler
-{
- private:
- Gem5SimControl& control;
-
- public:
- SCSlavePortHandler(Gem5SimControl& control) : control(control) {}
-
- ExternalSlave::Port *getExternalPort(const std::string &name,
- ExternalSlave &owner,
- const std::string &port_data);
-};
-
-}
-
-#endif // __SC_SLAVE_PORT_H__
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Matthias Jung
- * Abdul Mutaal Ahmad
- * Christian Menard
- */
-
-/**
- * @file
- *
- * Example top level file for SystemC-TLM integration with C++-only
- * instantiation.
- *
- */
-
-#include <systemc>
-#include <tlm>
-
-#include "sc_master_port.hh"
-#include "sc_slave_port.hh"
-#include "sim/cxx_config_ini.hh"
-#include "sim/init_signals.hh"
-#include "sim/stat_control.hh"
-#include "sim_control.hh"
-#include "stats.hh"
-
-// Define global string variable decalred in stats.hh
-std::string filename = "m5out/stats-systemc.txt";
-
-namespace Gem5SystemC
-{
-
-Gem5SimControl* Gem5SimControl::instance = nullptr;
-
-Gem5SimControl::Gem5SimControl(sc_core::sc_module_name name,
- const std::string& configFile,
- uint64_t simulationEnd,
- const std::string& gem5DebugFlags)
- : Gem5SystemC::Module(name),
- simulationEnd(simulationEnd)
-{
- SC_THREAD(run);
-
- if (instance != nullptr) {
- panic("Tried to instantiate Gem5SimControl more than once!\n");
- }
- instance = this;
-
- cxxConfigInit();
-
- // register the systemc slave and master port handler
- ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
- ExternalMaster::registerHandler("tlm_master",
- new SCMasterPortHandler(*this));
-
- Trace::setDebugLogger(&logger);
-
- Gem5SystemC::setTickFrequency();
- sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
-
- Gem5SystemC::Module::setupEventQueues(*this);
- initSignals();
-
- Stats::initSimStats();
- Stats::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
-
- Trace::enable();
-
- CxxConfigFileBase* conf = new CxxIniFile();
-
- if (configFile.empty()) {
- std::cerr << "No gem5 config file specified!\n";
- std::exit(EXIT_FAILURE);
- }
-
- if (!conf->load(configFile.c_str())) {
- std::cerr << "Can't open config file: " << configFile << '\n';
- std::exit(EXIT_FAILURE);
- }
-
- config_manager = new CxxConfigManager(*conf);
-
- // parse debug flags string and clear/set flags accordingly
- std::stringstream ss;
- ss.str(gem5DebugFlags);
- std::string flag;
- while (std::getline(ss, flag, ' ')) {
- if (flag.at(0) == '-') {
- flag.erase(0, 1); // remove the '-'
- clearDebugFlag(flag.c_str());
- }
- else {
- setDebugFlag(flag.c_str());
- }
- }
-
- CxxConfig::statsEnable();
- getEventQueue(0)->dump();
-
- try {
- config_manager->instantiate();
- } catch (CxxConfigManager::Exception &e) {
- std::cerr << "Config problem in sim object "
- << e.name << ": " << e.message << "\n";
- std::exit(EXIT_FAILURE);
- }
-}
-
-void
-Gem5SimControl::end_of_elaboration()
-{
- try {
- config_manager->initState();
- config_manager->startup();
- } catch (CxxConfigManager::Exception &e) {
- std::cerr << "Config problem in sim object "
- << e.name << ": " << e.message << "\n";
- std::exit(EXIT_FAILURE);
- }
-}
-
-void
-Gem5SimControl::run()
-{
- // notify callback
- beforeSimulate();
-
- GlobalSimLoopExitEvent *exit_event = NULL;
-
- if (simulationEnd == 0) {
- exit_event = simulate();
- } else {
- exit_event = simulate(simulationEnd);
- }
-
- std::cerr << "Exit at tick " << curTick()
- << ", cause: " << exit_event->getCause() << '\n';
-
- getEventQueue(0)->dump();
-
- // notify callback
- afterSimulate();
-
-#if TRY_CLEAN_DELETE
- config_manager->deleteObjects();
-#endif
-}
-
-void
-Gem5SimControl::registerSlavePort(const std::string& name, SCSlavePort* port)
-{
- if (slavePorts.find(name) == slavePorts.end()) {
- slavePorts[name] = port;
- } else {
- std::cerr << "Slave Port " << name << " is already registered!\n";
- std::exit(EXIT_FAILURE);
- }
-}
-
-void
-Gem5SimControl::registerMasterPort(const std::string& name, SCMasterPort* port)
-{
- if (masterPorts.find(name) == masterPorts.end()) {
- masterPorts[name] = port;
- } else {
- std::cerr << "Master Port " << name << " is already registered!\n";
- std::exit(EXIT_FAILURE);
- }
-}
-
-SCSlavePort*
-Gem5SimControl::getSlavePort(const std::string& name)
-{
- if (slavePorts.find(name) == slavePorts.end()) {
- std::cerr << "Slave Port " << name << " was not found!\n";
- std::exit(EXIT_FAILURE);
- }
-
- return slavePorts.at(name);
-}
-
-SCMasterPort*
-Gem5SimControl::getMasterPort(const std::string& name)
-{
- if (masterPorts.find(name) == masterPorts.end()) {
- std::cerr << "Master Port " << name << " was not found!\n";
- std::exit(EXIT_FAILURE);
- }
-
- return masterPorts.at(name);
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2015, University of Kaiserslautern
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Matthias Jung
- * Christian Menard
- */
-
-#ifndef __SC_SIM_CONTROL_HH__
-#define __SC_SIM_CONTROL_HH__
-
-#include <tlm_utils/simple_target_socket.h>
-
-#include <systemc>
-#include <tlm>
-
-#include "sc_logger.hh"
-#include "sc_module.hh"
-#include "sim/cxx_manager.hh"
-#include "sim/system.hh"
-#include "sim_control_if.hh"
-
-namespace Gem5SystemC
-{
-
-/**
- * This is the central SystemC module that orchestrates the gem5 simulation.
- *
- * The module is responsible for loading the configuration file, setting up and
- * maintaining the event queues, as well as starting and ending the simulation.
- * While it is mandatory to have one instance of this class for running a gem5
- * simulation in SystemC, it is not allowed to have multiple instances!
- */
-class Gem5SimControl : public Module, public Gem5SimControlInterface
-{
- protected:
- CxxConfigManager* config_manager;
- Gem5SystemC::Logger logger;
-
- Tick simulationEnd;
-
- /*
- * Keep track of the slave and master ports that are created by gem5
- * according to the config file.
- */
- std::map<const std::string, SCSlavePort*> slavePorts;
- std::map<const std::string, SCMasterPort*> masterPorts;
-
- /// Pointer to a previously created instance.
- static Gem5SimControl* instance;
-
- /** A callback that is called from the run thread before gem5 simulation is
- * started.
- *
- * A derived class may use this to perform any additional initializations
- * prior simulation.
- */
- virtual void beforeSimulate() {}
-
- /** A callback that is called from the run thread after gem5 simulation
- * completed.
- *
- * A derived class may use this to perform any additional tasks after gem5
- * exits. For instance, a derived class could use this to call sc_stop().
- */
- virtual void afterSimulate() {}
-
- public:
- SC_HAS_PROCESS(Gem5SimControl);
-
- /**
- * Constructor.
- *
- * This class has a public constructor although the class is actually a
- * singleton. The public constructor is required to ensure compatibility
- * to external SystemC based tools. For the same reason, the constructor
- * parameters are basic types (int, string).
- *
- * @param configFile location of the gem5 configuration file
- * @param simulationEnd number of ticks to simulate
- * @param gem5DebugFlags a space separated list of gem5 debug flags to be
- * set, a prepended '-' clears the flag
- */
- Gem5SimControl(sc_core::sc_module_name name,
- const std::string& configFile,
- uint64_t simulationEnd,
- const std::string& gem5DebugFlags);
-
- void registerSlavePort(const std::string& name, SCSlavePort* port);
- void registerMasterPort(const std::string& name, SCMasterPort* port);
- SCSlavePort* getSlavePort(const std::string& name) override;
- SCMasterPort* getMasterPort(const std::string& name) override;
-
- void end_of_elaboration();
-
- void run();
-};
-
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2017, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#ifndef __SC_SIM_CONTROL_IF_HH__
-#define __SC_SIM_CONTROL_IF_HH__
-
-#include <systemc>
-
-namespace Gem5SystemC
-{
-
-// forward declerations
-class SCSlavePort;
-class SCMasterPort;
-
-class Gem5SimControlInterface : public sc_core::sc_interface
-{
- public:
- virtual SCSlavePort* getSlavePort(const std::string& name) = 0;
- virtual SCMasterPort* getMasterPort(const std::string& name) = 0;
-};
-
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#include "sc_slave_port.hh"
-#include "sim_control.hh"
-#include "slave_transactor.hh"
-
-namespace Gem5SystemC
-{
-
-Gem5SlaveTransactor::Gem5SlaveTransactor(sc_core::sc_module_name name,
- const std::string& portName)
- : sc_core::sc_module(name),
- socket(portName.c_str()),
- sim_control("sim_control"),
- portName(portName)
-{
- if (portName.empty()) {
- SC_REPORT_ERROR(name, "No port name specified!\n");
- }
-}
-
-void
-Gem5SlaveTransactor::before_end_of_elaboration()
-{
- auto* port = sim_control->getSlavePort(portName);
-
- port->bindToTransactor(this);
-}
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#ifndef __GEM5_SLAVE_TRANSACTOR_HH__
-#define __GEM5_SLAVE_TRANSACTOR_HH__
-
-#include <tlm_utils/simple_initiator_socket.h>
-
-#include <systemc>
-#include <tlm>
-
-#include "sc_slave_port.hh"
-#include "sim_control_if.hh"
-
-namespace Gem5SystemC
-{
-
-class Gem5SlaveTransactor : public sc_core::sc_module
-{
- public:
- // module interface
- tlm_utils::simple_initiator_socket<SCSlavePort> socket;
- sc_core::sc_port<Gem5SimControlInterface> sim_control;
-
- private:
- std::string portName;
-
- public:
- SC_HAS_PROCESS(Gem5SlaveTransactor);
-
- Gem5SlaveTransactor(sc_core::sc_module_name name,
- const std::string& portName);
-
- void before_end_of_elaboration();
-};
-
-}
-
-#endif
--- /dev/null
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+Import('env')
+
+env = env.Clone()
+
+gem5_root = env['GEM5_ROOT']
+
+systemc_src = []
+systemc_src += Install('.', gem5_root + '/util/systemc/sc_gem5_control.cc'),
+systemc_src += Install('.', gem5_root + '/util/systemc/sc_logger.cc'),
+systemc_src += Install('.', gem5_root + '/util/systemc/sc_module.cc'),
+systemc_src += Install('.', gem5_root + '/util/systemc/stats.cc'),
+
+tlm_src = []
+tlm_src += [File('master_transactor.cc')]
+tlm_src += [File('sc_ext.cc')]
+tlm_src += [File('sc_master_port.cc')]
+tlm_src += [File('sc_mm.cc')]
+tlm_src += [File('sc_slave_port.cc')]
+tlm_src += [File('sim_control.cc')]
+tlm_src += [File('slave_transactor.cc')]
+
+tlm = env.Library('gem5_tlm', tlm_src + systemc_src)
+
+Return('tlm')
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include "master_transactor.hh"
+#include "sc_master_port.hh"
+#include "sim_control.hh"
+
+namespace Gem5SystemC
+{
+
+Gem5MasterTransactor::Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName)
+ : sc_core::sc_module(name),
+ socket(portName.c_str()),
+ sim_control("sim_control"),
+ portName(portName)
+{
+ if (portName.empty()) {
+ SC_REPORT_ERROR(name, "No port name specified!\n");
+ }
+}
+
+void
+Gem5MasterTransactor::before_end_of_elaboration()
+{
+ auto* port = sim_control->getMasterPort(portName);
+
+ port->bindToTransactor(this);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __GEM5_MASTER_TRANSACTOR_HH__
+#define __GEM5_MASTER_TRANSACTOR_HH__
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_master_port.hh"
+#include "sim_control_if.hh"
+
+namespace Gem5SystemC
+{
+
+class Gem5MasterTransactor : public sc_core::sc_module
+{
+ public:
+ // module interface
+ tlm_utils::simple_target_socket<SCMasterPort> socket;
+ sc_core::sc_port<Gem5SimControlInterface> sim_control;
+
+ private:
+ std::string portName;
+
+ public:
+ SC_HAS_PROCESS(Gem5MasterTransactor);
+
+ Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName);
+
+ void before_end_of_elaboration();
+};
+
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ * Matthias Jung
+ * Christian Menard
+ */
+
+#include "sc_ext.hh"
+
+using namespace tlm;
+
+namespace Gem5SystemC
+{
+
+Gem5Extension::Gem5Extension(PacketPtr packet)
+{
+ Packet = packet;
+ pipeThrough = false;
+}
+
+Gem5Extension& Gem5Extension::getExtension(const tlm_generic_payload *payload)
+{
+ Gem5Extension *result = NULL;
+ payload->get_extension(result);
+ sc_assert(result!=NULL);
+ return *result;
+}
+
+Gem5Extension& Gem5Extension::getExtension(const tlm_generic_payload &payload)
+{
+ return Gem5Extension::getExtension(&payload);
+}
+
+PacketPtr Gem5Extension::getPacket()
+{
+ return Packet;
+}
+
+tlm_extension_base* Gem5Extension::clone() const
+{
+ return new Gem5Extension(Packet);
+}
+
+void Gem5Extension::copy_from(const tlm_extension_base& ext)
+{
+ const Gem5Extension& cpyFrom = static_cast<const Gem5Extension&>(ext);
+ Packet = cpyFrom.Packet;
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ * Matthias Jung
+ * Christian Menard
+ */
+
+#ifndef __SC_EXT_HH__
+#define __SC_EXT_HH__
+
+#include <systemc.h>
+#include <tlm.h>
+
+#include <iostream>
+
+#include "mem/packet.hh"
+
+namespace Gem5SystemC
+{
+
+class Gem5Extension: public tlm::tlm_extension<Gem5Extension>
+{
+ public:
+ Gem5Extension(PacketPtr packet);
+
+ virtual tlm_extension_base* clone() const;
+ virtual void copy_from(const tlm_extension_base& ext);
+
+ static Gem5Extension&
+ getExtension(const tlm::tlm_generic_payload *payload);
+ static Gem5Extension&
+ getExtension(const tlm::tlm_generic_payload &payload);
+ PacketPtr getPacket();
+
+ bool isPipeThrough() const { return pipeThrough; }
+ void setPipeThrough() { pipeThrough = true; }
+
+ private:
+ PacketPtr Packet;
+ bool pipeThrough;
+};
+
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include <sstream>
+
+#include "master_transactor.hh"
+#include "params/ExternalMaster.hh"
+#include "sc_ext.hh"
+#include "sc_master_port.hh"
+#include "sim/system.hh"
+
+namespace Gem5SystemC
+{
+
+PacketPtr
+SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans)
+{
+ Request::Flags flags;
+ auto req = new Request(trans.get_address(), trans.get_data_length(), flags,
+ owner.masterId);
+
+ MemCmd cmd;
+
+ switch (trans.get_command()) {
+ case tlm::TLM_READ_COMMAND:
+ cmd = MemCmd::ReadReq;
+ break;
+ case tlm::TLM_WRITE_COMMAND:
+ cmd = MemCmd::WriteReq;
+ break;
+ default:
+ SC_REPORT_FATAL("SCMasterPort",
+ "received transaction with unsupported command");
+ }
+
+ /*
+ * Allocate a new Packet. The packet will be deleted when it returns from
+ * the gem5 world as a response.
+ */
+ auto pkt = new Packet(req, cmd);
+ pkt->dataStatic(trans.get_data_ptr());
+
+ return pkt;
+}
+
+void
+SCMasterPort::destroyPacket(PacketPtr pkt)
+{
+ delete pkt;
+}
+
+SCMasterPort::SCMasterPort(const std::string& name_,
+ const std::string& systemc_name,
+ ExternalMaster& owner_,
+ Gem5SimControl& simControl)
+ : ExternalMaster::Port(name_, owner_),
+ peq(this, &SCMasterPort::peq_cb),
+ waitForRetry(false),
+ pendingRequest(nullptr),
+ pendingPacket(nullptr),
+ needToSendRetry(false),
+ responseInProgress(false),
+ transactor(nullptr),
+ simControl(simControl)
+{
+ system =
+ dynamic_cast<const ExternalMasterParams*>(owner_.params())->system;
+}
+
+void
+SCMasterPort::bindToTransactor(Gem5MasterTransactor* transactor)
+{
+ sc_assert(this->transactor == nullptr);
+
+ this->transactor = transactor;
+
+ /*
+ * Register the TLM non-blocking interface when using gem5 Timing mode and
+ * the TLM blocking interface when using the gem5 Atomic mode.
+ * Then the magic (TM) in simple_target_socket automatically transforms
+ * non-blocking in blocking transactions and vice versa.
+ *
+ * NOTE: The mode may change during execution.
+ */
+ if (system->isTimingMode()) {
+ SC_REPORT_INFO("SCMasterPort", "register non-blocking interface");
+ transactor->socket.register_nb_transport_fw(this,
+ &SCMasterPort::nb_transport_fw);
+ } else if (system->isAtomicMode()) {
+ SC_REPORT_INFO("SCMasterPort", "register blocking interface");
+ transactor->socket.register_b_transport(this,
+ &SCMasterPort::b_transport);
+ } else {
+ panic("gem5 operates neither in Timing nor in Atomic mode");
+ }
+
+ transactor->socket.register_transport_dbg(this,
+ &SCMasterPort::transport_dbg);
+}
+
+void
+SCMasterPort::checkTransaction(tlm::tlm_generic_payload& trans)
+{
+ if (trans.is_response_error()) {
+ std::stringstream ss;
+ ss << "Transaction returned with error, response status = "
+ << trans.get_response_string();
+ SC_REPORT_ERROR("TLM-2", ss.str().c_str());
+ }
+}
+
+tlm::tlm_sync_enum
+SCMasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans,
+ tlm::tlm_phase& phase, sc_core::sc_time& delay)
+{
+ uint64_t adr = trans.get_address();
+ unsigned len = trans.get_data_length();
+ unsigned char* byteEnable = trans.get_byte_enable_ptr();
+ unsigned width = trans.get_streaming_width();
+
+ // check the transaction attributes for unsupported features ...
+ if (byteEnable != 0) {
+ trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
+ return tlm::TLM_COMPLETED;
+ }
+ if (width < len) { // is this a burst request?
+ trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
+ return tlm::TLM_COMPLETED;
+ }
+
+ // ... and queue the valid transaction
+ trans.acquire();
+ peq.notify(trans, phase, delay);
+ return tlm::TLM_ACCEPTED;
+}
+
+void
+SCMasterPort::peq_cb(tlm::tlm_generic_payload& trans,
+ const tlm::tlm_phase& phase)
+{
+ // catch up with SystemC time
+ simControl.catchup();
+ assert(curTick() == sc_core::sc_time_stamp().value());
+
+ switch (phase) {
+ case tlm::BEGIN_REQ:
+ handleBeginReq(trans);
+ break;
+ case tlm::END_RESP:
+ handleEndResp(trans);
+ break;
+ default:
+ panic("unimplemented phase in callback");
+ }
+
+ // the functions called above may have scheduled gem5 events
+ // -> notify the event loop handler
+ simControl.notify();
+}
+
+void
+SCMasterPort::handleBeginReq(tlm::tlm_generic_payload& trans)
+{
+ sc_assert(!waitForRetry);
+ sc_assert(pendingRequest == nullptr);
+ sc_assert(pendingPacket == nullptr);
+
+ trans.acquire();
+
+ PacketPtr pkt = nullptr;
+
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet. Otherwise, we
+ // generate a new packet based on the transaction.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ pkt = extension->getPacket();
+ } else {
+ pkt = generatePacket(trans);
+ }
+
+ auto tlmSenderState = new TlmSenderState(trans);
+ pkt->pushSenderState(tlmSenderState);
+
+ if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
+ sendEndReq(trans);
+ trans.release();
+ } else { // port is blocked -> wait for retry before sending END_REQ
+ waitForRetry = true;
+ pendingRequest = &trans;
+ pendingPacket = pkt;
+ }
+}
+
+void
+SCMasterPort::handleEndResp(tlm::tlm_generic_payload& trans)
+{
+ sc_assert(responseInProgress);
+
+ responseInProgress = false;
+
+ checkTransaction(trans);
+
+ if (needToSendRetry) {
+ sendRetryResp();
+ needToSendRetry = false;
+ }
+}
+
+void
+SCMasterPort::sendEndReq(tlm::tlm_generic_payload& trans)
+{
+ tlm::tlm_phase phase = tlm::END_REQ;
+ auto delay = sc_core::SC_ZERO_TIME;
+
+ auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
+ panic_if(status != tlm::TLM_ACCEPTED,
+ "Unexpected status after sending END_REQ");
+}
+
+void
+SCMasterPort::b_transport(tlm::tlm_generic_payload& trans,
+ sc_core::sc_time& t)
+{
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ PacketPtr pkt = nullptr;
+
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ pkt = extension->getPacket();
+ } else {
+ pkt = generatePacket(trans);
+ }
+
+ Tick ticks = sendAtomic(pkt);
+
+ // send an atomic request to gem5
+ panic_if(pkt->needsResponse() && !pkt->isResponse(),
+ "Packet sending failed!\n");
+
+ // one tick is a pico second
+ auto delay =
+ sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
+
+ // update time
+ t += delay;
+
+ if (extension != nullptr)
+ destroyPacket(pkt);
+
+ trans.set_response_status(tlm::TLM_OK_RESPONSE);
+}
+
+unsigned int
+SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans)
+{
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ sendFunctional(extension->getPacket());
+ } else {
+ auto pkt = generatePacket(trans);
+ sendFunctional(pkt);
+ destroyPacket(pkt);
+ }
+
+ return trans.get_data_length();
+}
+
+bool
+SCMasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
+ tlm::tlm_dmi& dmi_data)
+{
+ return false;
+}
+
+bool
+SCMasterPort::recvTimingResp(PacketPtr pkt)
+{
+ // exclusion rule
+ // We need to Wait for END_RESP before sending next BEGIN_RESP
+ if (responseInProgress) {
+ sc_assert(!needToSendRetry);
+ needToSendRetry = true;
+ return false;
+ }
+
+ sc_assert(pkt->isResponse());
+
+ /*
+ * Pay for annotated transport delays.
+ *
+ * See recvTimingReq in sc_slave_port.cc for a detailed description.
+ */
+ auto delay = sc_core::sc_time::from_value(pkt->payloadDelay);
+ // reset the delays
+ pkt->payloadDelay = 0;
+ pkt->headerDelay = 0;
+
+ auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
+ sc_assert(tlmSenderState != nullptr);
+
+ auto& trans = tlmSenderState->trans;
+
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ // clean up
+ delete tlmSenderState;
+
+ // If there is an extension the packet was piped through and we must not
+ // delete it. The packet travels back with the transaction.
+ if (extension == nullptr)
+ destroyPacket(pkt);
+ else
+ sc_assert(extension->isPipeThrough());
+
+ sendBeginResp(trans, delay);
+ trans.release();
+
+ return true;
+}
+
+void
+SCMasterPort::sendBeginResp(tlm::tlm_generic_payload& trans,
+ sc_core::sc_time& delay)
+{
+ tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
+ trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
+ auto status = transactor->socket->nb_transport_bw(trans, phase, delay);
+
+ if (status == tlm::TLM_COMPLETED ||
+ status == tlm::TLM_UPDATED && phase == tlm::END_RESP) {
+ // transaction completed -> no need to wait for tlm::END_RESP
+ responseInProgress = false;
+ } else if (status == tlm::TLM_ACCEPTED) {
+ // we need to wait for tlm::END_RESP
+ responseInProgress = true;
+ } else {
+ panic("Unexpected status after sending BEGIN_RESP");
+ }
+}
+
+void
+SCMasterPort::recvReqRetry()
+{
+ sc_assert(waitForRetry);
+ sc_assert(pendingRequest != nullptr);
+ sc_assert(pendingPacket != nullptr);
+
+ if (sendTimingReq(pendingPacket)) {
+ waitForRetry = false;
+ pendingPacket = nullptr;
+
+ auto& trans = *pendingRequest;
+ sendEndReq(trans);
+ trans.release();
+
+ pendingRequest = nullptr;
+ }
+}
+
+void
+SCMasterPort::recvRangeChange()
+{
+ SC_REPORT_WARNING("SCMasterPort",
+ "received address range change but ignored it");
+}
+
+ExternalMaster::Port*
+SCMasterPortHandler::getExternalPort(const std::string &name,
+ ExternalMaster &owner,
+ const std::string &port_data)
+{
+ // Create and register a new SystemC master port
+ auto* port = new SCMasterPort(name, port_data, owner, control);
+
+ control.registerMasterPort(port_data, port);
+
+ return port;
+}
+
+} // namespace Gem5SystemC
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __SC_MASTER_PORT_HH__
+#define __SC_MASTER_PORT_HH__
+
+#include <tlm_utils/peq_with_cb_and_phase.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "mem/external_master.hh"
+#include "sc_peq.hh"
+#include "sim_control.hh"
+
+namespace Gem5SystemC
+{
+
+// forward declaration
+class Gem5MasterTransactor;
+
+/**
+ * This is a gem5 master port that translates TLM transactions to gem5 packets.
+ *
+ * Upon receiving a TLM transaction (b_transport, nb_transport_fw,
+ * dbg_transport) the port generates a gem5 packet and initializes the packet
+ * with information from the transaction payload. The original TLM payload is
+ * added as a sender state to the gem5 packet. This way the payload can be
+ * restored when the response packet arrives at the port.
+ *
+ * Special care is required, when the TLM transaction originates from a
+ * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
+ * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
+ * interconnect. In this case, the master port restores the original packet
+ * from the payload extension (added by the SCSlavePort) and forwards it to the
+ * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
+ *
+ * If gem5 operates in atomic mode, the master port registers the TLM blocking
+ * interface and automatically translates non-blocking requests to blocking.
+ * If gem5 operates in timing mode, the transactor registers the non-blocking
+ * interface. Then, the transactor automatically translated blocking requests.
+ * It is assumed that the mode (atomic/timing) does not change during
+ * execution.
+ */
+class SCMasterPort : public ExternalMaster::Port
+{
+ private:
+ struct TlmSenderState : public Packet::SenderState
+ {
+ tlm::tlm_generic_payload& trans;
+ TlmSenderState(tlm::tlm_generic_payload& trans)
+ : trans(trans)
+ {
+ }
+ };
+
+ tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
+
+ bool waitForRetry;
+ tlm::tlm_generic_payload* pendingRequest;
+ PacketPtr pendingPacket;
+
+ bool needToSendRetry;
+
+ bool responseInProgress;
+
+ Gem5MasterTransactor* transactor;
+
+ System* system;
+
+ Gem5SimControl& simControl;
+
+ protected:
+ // payload event call back
+ void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
+
+ // The TLM target interface
+ tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
+ tlm::tlm_phase& phase,
+ sc_core::sc_time& t);
+ void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
+ unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
+ bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
+ tlm::tlm_dmi& dmi_data);
+
+ // Gem5 SCMasterPort interface
+ bool recvTimingResp(PacketPtr pkt);
+ void recvReqRetry();
+ void recvRangeChange();
+
+ public:
+ SCMasterPort(const std::string& name_,
+ const std::string& systemc_name,
+ ExternalMaster& owner_,
+ Gem5SimControl& simControl);
+
+ void bindToTransactor(Gem5MasterTransactor* transactor);
+
+ friend PayloadEvent<SCMasterPort>;
+
+ private:
+ void sendEndReq(tlm::tlm_generic_payload& trans);
+ void sendBeginResp(tlm::tlm_generic_payload& trans,
+ sc_core::sc_time& delay);
+
+ void handleBeginReq(tlm::tlm_generic_payload& trans);
+ void handleEndResp(tlm::tlm_generic_payload& trans);
+
+ PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
+ void destroyPacket(PacketPtr pkt);
+
+ void checkTransaction(tlm::tlm_generic_payload& trans);
+};
+
+class SCMasterPortHandler : public ExternalMaster::Handler
+{
+ private:
+ Gem5SimControl& control;
+
+ public:
+ SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
+
+ ExternalMaster::Port *getExternalPort(const std::string &name,
+ ExternalMaster &owner,
+ const std::string &port_data);
+};
+
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ * Robert Gernhardt
+ * Matthias Jung
+ */
+
+#include <iostream>
+
+#include "sc_mm.hh"
+
+using namespace std;
+
+namespace Gem5SystemC
+{
+
+MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0)
+{
+
+}
+
+MemoryManager::~MemoryManager()
+{
+ for (gp* payload: freePayloads) {
+ delete payload;
+ numberOfFrees++;
+ }
+}
+
+gp*
+MemoryManager::allocate()
+{
+ if (freePayloads.empty()) {
+ numberOfAllocations++;
+ return new gp(this);
+ } else {
+ gp* result = freePayloads.back();
+ freePayloads.pop_back();
+ return result;
+ }
+}
+
+void
+MemoryManager::free(gp* payload)
+{
+ payload->reset(); //clears all extensions
+ freePayloads.push_back(payload);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ * Robert Gernhardt
+ * Matthias Jung
+ */
+
+#ifndef __SC_MM_HH__
+#define __SC_MM_HH__
+
+#include <tlm.h>
+
+#include <vector>
+
+namespace Gem5SystemC
+{
+
+typedef tlm::tlm_generic_payload gp;
+
+class MemoryManager : public tlm::tlm_mm_interface
+{
+ public:
+ MemoryManager();
+ virtual ~MemoryManager();
+ virtual gp* allocate();
+ virtual void free(gp* payload);
+
+ private:
+ unsigned int numberOfAllocations;
+ unsigned int numberOfFrees;
+ std::vector<gp*> freePayloads;
+};
+
+}
+
+#endif /* __SC_MM_HH__ */
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Christian Menard
+ */
+
+#ifndef PAYLOAD_EVENT_H_
+#define PAYLOAD_EVENT_H_
+
+// TLM includes
+#include <tlm.h>
+
+// gem5 includes
+#include <sim/eventq.hh>
+
+namespace Gem5SystemC {
+/**
+ * A 'Fake Payload Event Queue', similar to the TLM PEQs. This helps the
+ * transactors to schedule events in gem5.
+ */
+template <typename OWNER>
+class PayloadEvent : public Event
+{
+ public:
+ OWNER& port;
+ const std::string eventName;
+ void (OWNER::*handler)(PayloadEvent<OWNER>* pe,
+ tlm::tlm_generic_payload& trans,
+ const tlm::tlm_phase& phase);
+
+ protected:
+ tlm::tlm_generic_payload* t;
+ tlm::tlm_phase p;
+
+ void process() { (port.*handler)(this, *t, p); }
+
+ public:
+ const std::string name() const { return eventName; }
+
+ PayloadEvent(OWNER& port_,
+ void (OWNER::*handler_)(PayloadEvent<OWNER>* pe,
+ tlm::tlm_generic_payload& trans,
+ const tlm::tlm_phase& phase),
+ const std::string& event_name)
+ : port(port_)
+ , eventName(event_name)
+ , handler(handler_)
+ {
+ }
+
+ /// Schedule an event into gem5
+ void notify(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase,
+ const sc_core::sc_time& delay)
+ {
+ assert(!scheduled());
+
+ t = &trans;
+ p = phase;
+
+ /**
+ * Get time from SystemC as this will always be more up to date
+ * than gem5's
+ */
+ Tick nextEventTick = sc_core::sc_time_stamp().value() + delay.value();
+
+ port.owner.wakeupEventQueue(nextEventTick);
+ port.owner.schedule(this, nextEventTick);
+ }
+};
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Abdul Mutaal Ahmad
+ * Christian Menard
+ */
+
+#include "sc_ext.hh"
+#include "sc_mm.hh"
+#include "sc_slave_port.hh"
+#include "slave_transactor.hh"
+
+namespace Gem5SystemC
+{
+
+/**
+ * Instantiate a tlm memory manager that takes care about all the
+ * tlm transactions in the system
+ */
+MemoryManager mm;
+
+/**
+ * Convert a gem5 packet to a TLM payload by copying all the relevant
+ * information to a previously allocated tlm payload
+ */
+void
+packet2payload(PacketPtr packet, tlm::tlm_generic_payload &trans)
+{
+ trans.set_address(packet->getAddr());
+
+ /* Check if this transaction was allocated by mm */
+ sc_assert(trans.has_mm());
+
+ unsigned int size = packet->getSize();
+ unsigned char *data = packet->getPtr<unsigned char>();
+
+ trans.set_data_length(size);
+ trans.set_streaming_width(size);
+ trans.set_data_ptr(data);
+
+ if (packet->isRead()) {
+ trans.set_command(tlm::TLM_READ_COMMAND);
+ }
+ else if (packet->isInvalidate()) {
+ /* Do nothing */
+ } else if (packet->isWrite()) {
+ trans.set_command(tlm::TLM_WRITE_COMMAND);
+ } else {
+ SC_REPORT_FATAL("SCSlavePort", "No R/W packet");
+ }
+}
+
+/**
+ * Similar to TLM's blocking transport (LT)
+ */
+Tick
+SCSlavePort::recvAtomic(PacketPtr packet)
+{
+ CAUGHT_UP;
+ SC_REPORT_INFO("SCSlavePort", "recvAtomic hasn't been tested much");
+
+ panic_if(packet->cacheResponding(), "Should not see packets where cache "
+ "is responding");
+
+ panic_if(!(packet->isRead() || packet->isWrite()),
+ "Should only see read and writes at TLM memory\n");
+
+
+ sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+
+
+ /* Prepare the transaction */
+ tlm::tlm_generic_payload * trans = mm.allocate();
+ trans->acquire();
+ packet2payload(packet, *trans);
+
+ /* Attach the packet pointer to the TLM transaction to keep track */
+ Gem5Extension* extension = new Gem5Extension(packet);
+ trans->set_auto_extension(extension);
+
+ /* Execute b_transport: */
+ if (packet->cmd == MemCmd::SwapReq) {
+ SC_REPORT_FATAL("SCSlavePort", "SwapReq not supported");
+ } else if (packet->isRead()) {
+ transactor->socket->b_transport(*trans, delay);
+ } else if (packet->isInvalidate()) {
+ // do nothing
+ } else if (packet->isWrite()) {
+ transactor->socket->b_transport(*trans, delay);
+ } else {
+ SC_REPORT_FATAL("SCSlavePort", "Typo of request not supported");
+ }
+
+ if (packet->needsResponse()) {
+ packet->makeResponse();
+ }
+
+ trans->release();
+
+ return delay.value();
+}
+
+/**
+ * Similar to TLM's debug transport
+ */
+void
+SCSlavePort::recvFunctional(PacketPtr packet)
+{
+ /* Prepare the transaction */
+ tlm::tlm_generic_payload * trans = mm.allocate();
+ trans->acquire();
+ packet2payload(packet, *trans);
+
+ /* Attach the packet pointer to the TLM transaction to keep track */
+ Gem5Extension* extension = new Gem5Extension(packet);
+ trans->set_auto_extension(extension);
+
+ /* Execute Debug Transport: */
+ unsigned int bytes = transactor->socket->transport_dbg(*trans);
+ if (bytes != trans->get_data_length()) {
+ SC_REPORT_FATAL("SCSlavePort","debug transport was not completed");
+ }
+
+ trans->release();
+}
+
+bool
+SCSlavePort::recvTimingSnoopResp(PacketPtr packet)
+{
+ /* Snooping should be implemented with tlm_dbg_transport */
+ SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvTimingSnoopResp");
+ return false;
+}
+
+void
+SCSlavePort::recvFunctionalSnoop(PacketPtr packet)
+{
+ /* Snooping should be implemented with tlm_dbg_transport */
+ SC_REPORT_FATAL("SCSlavePort","unimplemented func.: recvFunctionalSnoop");
+}
+
+/**
+ * Similar to TLM's non-blocking transport (AT)
+ */
+bool
+SCSlavePort::recvTimingReq(PacketPtr packet)
+{
+ CAUGHT_UP;
+
+ panic_if(packet->cacheResponding(), "Should not see packets where cache "
+ "is responding");
+
+ panic_if(!(packet->isRead() || packet->isWrite()),
+ "Should only see read and writes at TLM memory\n");
+
+
+ /* We should never get a second request after noting that a retry is
+ * required */
+ sc_assert(!needToSendRequestRetry);
+
+ /* Remember if a request comes in while we're blocked so that a retry
+ * can be sent to gem5 */
+ if (blockingRequest) {
+ needToSendRequestRetry = true;
+ return false;
+ }
+
+ /* NOTE: normal tlm is blocking here. But in our case we return false
+ * and tell gem5 when a retry can be done. This is the main difference
+ * in the protocol:
+ * if (requestInProgress)
+ * {
+ * wait(endRequestEvent);
+ * }
+ * requestInProgress = trans;
+ */
+
+ /* Prepare the transaction */
+ tlm::tlm_generic_payload * trans = mm.allocate();
+ trans->acquire();
+ packet2payload(packet, *trans);
+
+ /* Attach the packet pointer to the TLM transaction to keep track */
+ Gem5Extension* extension = new Gem5Extension(packet);
+ trans->set_auto_extension(extension);
+
+ /*
+ * Pay for annotated transport delays.
+ *
+ * The header delay marks the point in time, when the packet first is seen
+ * by the transactor. This is the point int time, when the transactor needs
+ * to send the BEGIN_REQ to the SystemC world.
+ *
+ * NOTE: We drop the payload delay here. Normally, the receiver would be
+ * responsible for handling the payload delay. In this case, however,
+ * the receiver is a SystemC module and has no notion of the gem5
+ * transport protocol and we cannot simply forward the
+ * payload delay to the receiving module. Instead, we expect the
+ * receiving SystemC module to model the payload delay by deferring
+ * the END_REQ. This could lead to incorrect delays, if the XBar
+ * payload delay is longer than the time the receiver needs to accept
+ * the request (time between BEGIN_REQ and END_REQ).
+ *
+ * TODO: We could detect the case described above by remembering the
+ * payload delay and comparing it to the time between BEGIN_REQ and
+ * END_REQ. Then, a warning should be printed.
+ */
+ auto delay = sc_core::sc_time::from_value(packet->payloadDelay);
+ // reset the delays
+ packet->payloadDelay = 0;
+ packet->headerDelay = 0;
+
+ /* Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
+ * Standard Page 507 for a visualisation of the procedure */
+ tlm::tlm_phase phase = tlm::BEGIN_REQ;
+ tlm::tlm_sync_enum status;
+ status = transactor->socket->nb_transport_fw(*trans, phase, delay);
+ /* Check returned value: */
+ if (status == tlm::TLM_ACCEPTED) {
+ sc_assert(phase == tlm::BEGIN_REQ);
+ /* Accepted but is now blocking until END_REQ (exclusion rule)*/
+ blockingRequest = trans;
+ } else if (status == tlm::TLM_UPDATED) {
+ /* The Timing annotation must be honored: */
+ sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
+
+ PayloadEvent<SCSlavePort> * pe;
+ pe = new PayloadEvent<SCSlavePort>(*this,
+ &SCSlavePort::pec, "PEQ");
+ pe->notify(*trans, phase, delay);
+ } else if (status == tlm::TLM_COMPLETED) {
+ /* Transaction is over nothing has do be done. */
+ sc_assert(phase == tlm::END_RESP);
+ trans->release();
+ }
+
+ return true;
+}
+
+void
+SCSlavePort::pec(
+ PayloadEvent<SCSlavePort> * pe,
+ tlm::tlm_generic_payload& trans,
+ const tlm::tlm_phase& phase)
+{
+ sc_time delay;
+
+ if (phase == tlm::END_REQ ||
+ &trans == blockingRequest && phase == tlm::BEGIN_RESP) {
+ sc_assert(&trans == blockingRequest);
+ blockingRequest = NULL;
+
+ /* Did another request arrive while blocked, schedule a retry */
+ if (needToSendRequestRetry) {
+ needToSendRequestRetry = false;
+ sendRetryReq();
+ }
+ }
+ if (phase == tlm::BEGIN_RESP)
+ {
+ CAUGHT_UP;
+
+ auto& extension = Gem5Extension::getExtension(trans);
+ auto packet = extension.getPacket();
+
+ sc_assert(!blockingResponse);
+
+ bool need_retry = false;
+
+ /*
+ * If the packet was piped through and needs a response, we don't need
+ * to touch the packet and can forward it directly as a response.
+ * Otherwise, we need to make a response and send the transformed
+ * packet.
+ */
+ if (extension.isPipeThrough()) {
+ if (packet->isResponse()) {
+ need_retry = !sendTimingResp(packet);
+ }
+ } else if (packet->needsResponse()) {
+ packet->makeResponse();
+ need_retry = !sendTimingResp(packet);
+ }
+
+ if (need_retry) {
+ blockingResponse = &trans;
+ } else {
+ if (phase == tlm::BEGIN_RESP) {
+ /* Send END_RESP and we're finished: */
+ tlm::tlm_phase fw_phase = tlm::END_RESP;
+ sc_time delay = SC_ZERO_TIME;
+ transactor->socket->nb_transport_fw(trans, fw_phase, delay);
+ /* Release the transaction with all the extensions */
+ trans.release();
+ }
+ }
+ }
+ delete pe;
+}
+
+void
+SCSlavePort::recvRespRetry()
+{
+ CAUGHT_UP;
+
+ /* Retry a response */
+ sc_assert(blockingResponse);
+
+ tlm::tlm_generic_payload *trans = blockingResponse;
+ blockingResponse = NULL;
+ PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();
+
+ bool need_retry = !sendTimingResp(packet);
+
+ sc_assert(!need_retry);
+
+ sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+ tlm::tlm_phase phase = tlm::END_RESP;
+ transactor->socket->nb_transport_fw(*trans, phase, delay);
+ // Release transaction with all the extensions
+ trans->release();
+}
+
+tlm::tlm_sync_enum
+SCSlavePort::nb_transport_bw(tlm::tlm_generic_payload& trans,
+ tlm::tlm_phase& phase,
+ sc_core::sc_time& delay)
+{
+ PayloadEvent<SCSlavePort> * pe;
+ pe = new PayloadEvent<SCSlavePort>(*this, &SCSlavePort::pec, "PE");
+ pe->notify(trans, phase, delay);
+ return tlm::TLM_ACCEPTED;
+}
+
+SCSlavePort::SCSlavePort(const std::string &name_,
+ const std::string &systemc_name,
+ ExternalSlave &owner_) :
+ ExternalSlave::Port(name_, owner_),
+ blockingRequest(NULL),
+ needToSendRequestRetry(false),
+ blockingResponse(NULL),
+ transactor(nullptr)
+{
+}
+
+void
+SCSlavePort::bindToTransactor(Gem5SlaveTransactor* transactor)
+{
+ sc_assert(this->transactor == nullptr);
+
+ this->transactor = transactor;
+
+ transactor->socket.register_nb_transport_bw(this,
+ &SCSlavePort::nb_transport_bw);
+}
+
+ExternalSlave::Port*
+SCSlavePortHandler::getExternalPort(const std::string &name,
+ ExternalSlave &owner,
+ const std::string &port_data)
+{
+ // Create and register a new SystemC slave port
+ auto* port = new SCSlavePort(name, port_data, owner);
+
+ control.registerSlavePort(port_data, port);
+
+ return port;
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Christian Menard
+ */
+
+#ifndef __SC_SLAVE_PORT_HH__
+#define __SC_SLAVE_PORT_HH__
+
+#include <systemc>
+#include <tlm>
+
+#include "mem/external_slave.hh"
+#include "sc_mm.hh"
+#include "sc_peq.hh"
+#include "sim_control.hh"
+
+namespace Gem5SystemC
+{
+
+// forward declaration
+class Gem5SlaveTransactor;
+
+/**
+ * Test that gem5 is at the same time as SystemC
+ */
+#define CAUGHT_UP do { \
+ assert(curTick() == sc_core::sc_time_stamp().value()); \
+} while (0)
+
+/**
+ * This is a gem5 slave port that translates gem5 packets to TLM transactions.
+ *
+ * Upon receiving a packet (recvAtomic, recvTiningReq, recvFunctional) the port
+ * creates a new TLM payload and initializes it with information from the gem5
+ * packet. The original packet is added as an extension to the TLM payload.
+ * Then the port issues a TLM transaction in the SystemC world. By storing the
+ * original packet as a payload extension, the packet can be restored and send
+ * back to the gem5 world upon receiving a response from the SystemC world.
+ */
+class SCSlavePort : public ExternalSlave::Port
+{
+ public:
+ /** One instance of pe and the related callback needed */
+ //payloadEvent<SCSlavePort> pe;
+ void pec(PayloadEvent<SCSlavePort> * pe,
+ tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
+
+ /**
+ * A transaction after BEGIN_REQ has been sent but before END_REQ, which
+ * is blocking the request channel (Exlusion Rule, see IEEE1666)
+ */
+ tlm::tlm_generic_payload *blockingRequest;
+
+ /**
+ * Did another gem5 request arrive while currently blocked?
+ * This variable is needed when a retry should happen
+ */
+ bool needToSendRequestRetry;
+
+ /**
+ * A response which has been asked to retry by gem5 and so is blocking
+ * the response channel
+ */
+ tlm::tlm_generic_payload *blockingResponse;
+
+ protected:
+ /** The gem5 Port slave interface */
+ Tick recvAtomic(PacketPtr packet);
+ void recvFunctional(PacketPtr packet);
+ bool recvTimingReq(PacketPtr packet);
+ bool recvTimingSnoopResp(PacketPtr packet);
+ void recvRespRetry();
+ void recvFunctionalSnoop(PacketPtr packet);
+
+ Gem5SlaveTransactor* transactor;
+
+ public:
+ /** The TLM initiator interface */
+ tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
+ tlm::tlm_phase& phase,
+ sc_core::sc_time& t);
+
+ SCSlavePort(const std::string &name_,
+ const std::string &systemc_name,
+ ExternalSlave &owner_);
+
+ void bindToTransactor(Gem5SlaveTransactor* transactor);
+
+ friend PayloadEvent<SCSlavePort>;
+};
+
+class SCSlavePortHandler : public ExternalSlave::Handler
+{
+ private:
+ Gem5SimControl& control;
+
+ public:
+ SCSlavePortHandler(Gem5SimControl& control) : control(control) {}
+
+ ExternalSlave::Port *getExternalPort(const std::string &name,
+ ExternalSlave &owner,
+ const std::string &port_data);
+};
+
+}
+
+#endif // __SC_SLAVE_PORT_H__
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Abdul Mutaal Ahmad
+ * Christian Menard
+ */
+
+/**
+ * @file
+ *
+ * Example top level file for SystemC-TLM integration with C++-only
+ * instantiation.
+ *
+ */
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_master_port.hh"
+#include "sc_slave_port.hh"
+#include "sim/cxx_config_ini.hh"
+#include "sim/init_signals.hh"
+#include "sim/stat_control.hh"
+#include "sim_control.hh"
+#include "stats.hh"
+
+// Define global string variable decalred in stats.hh
+std::string filename = "m5out/stats-systemc.txt";
+
+namespace Gem5SystemC
+{
+
+Gem5SimControl* Gem5SimControl::instance = nullptr;
+
+Gem5SimControl::Gem5SimControl(sc_core::sc_module_name name,
+ const std::string& configFile,
+ uint64_t simulationEnd,
+ const std::string& gem5DebugFlags)
+ : Gem5SystemC::Module(name),
+ simulationEnd(simulationEnd)
+{
+ SC_THREAD(run);
+
+ if (instance != nullptr) {
+ panic("Tried to instantiate Gem5SimControl more than once!\n");
+ }
+ instance = this;
+
+ cxxConfigInit();
+
+ // register the systemc slave and master port handler
+ ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
+ ExternalMaster::registerHandler("tlm_master",
+ new SCMasterPortHandler(*this));
+
+ Trace::setDebugLogger(&logger);
+
+ Gem5SystemC::setTickFrequency();
+ sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
+
+ Gem5SystemC::Module::setupEventQueues(*this);
+ initSignals();
+
+ Stats::initSimStats();
+ Stats::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
+
+ Trace::enable();
+
+ CxxConfigFileBase* conf = new CxxIniFile();
+
+ if (configFile.empty()) {
+ std::cerr << "No gem5 config file specified!\n";
+ std::exit(EXIT_FAILURE);
+ }
+
+ if (!conf->load(configFile.c_str())) {
+ std::cerr << "Can't open config file: " << configFile << '\n';
+ std::exit(EXIT_FAILURE);
+ }
+
+ config_manager = new CxxConfigManager(*conf);
+
+ // parse debug flags string and clear/set flags accordingly
+ std::stringstream ss;
+ ss.str(gem5DebugFlags);
+ std::string flag;
+ while (std::getline(ss, flag, ' ')) {
+ if (flag.at(0) == '-') {
+ flag.erase(0, 1); // remove the '-'
+ clearDebugFlag(flag.c_str());
+ }
+ else {
+ setDebugFlag(flag.c_str());
+ }
+ }
+
+ CxxConfig::statsEnable();
+ getEventQueue(0)->dump();
+
+ try {
+ config_manager->instantiate();
+ } catch (CxxConfigManager::Exception &e) {
+ std::cerr << "Config problem in sim object "
+ << e.name << ": " << e.message << "\n";
+ std::exit(EXIT_FAILURE);
+ }
+}
+
+void
+Gem5SimControl::end_of_elaboration()
+{
+ try {
+ config_manager->initState();
+ config_manager->startup();
+ } catch (CxxConfigManager::Exception &e) {
+ std::cerr << "Config problem in sim object "
+ << e.name << ": " << e.message << "\n";
+ std::exit(EXIT_FAILURE);
+ }
+}
+
+void
+Gem5SimControl::run()
+{
+ // notify callback
+ beforeSimulate();
+
+ GlobalSimLoopExitEvent *exit_event = NULL;
+
+ if (simulationEnd == 0) {
+ exit_event = simulate();
+ } else {
+ exit_event = simulate(simulationEnd);
+ }
+
+ std::cerr << "Exit at tick " << curTick()
+ << ", cause: " << exit_event->getCause() << '\n';
+
+ getEventQueue(0)->dump();
+
+ // notify callback
+ afterSimulate();
+
+#if TRY_CLEAN_DELETE
+ config_manager->deleteObjects();
+#endif
+}
+
+void
+Gem5SimControl::registerSlavePort(const std::string& name, SCSlavePort* port)
+{
+ if (slavePorts.find(name) == slavePorts.end()) {
+ slavePorts[name] = port;
+ } else {
+ std::cerr << "Slave Port " << name << " is already registered!\n";
+ std::exit(EXIT_FAILURE);
+ }
+}
+
+void
+Gem5SimControl::registerMasterPort(const std::string& name, SCMasterPort* port)
+{
+ if (masterPorts.find(name) == masterPorts.end()) {
+ masterPorts[name] = port;
+ } else {
+ std::cerr << "Master Port " << name << " is already registered!\n";
+ std::exit(EXIT_FAILURE);
+ }
+}
+
+SCSlavePort*
+Gem5SimControl::getSlavePort(const std::string& name)
+{
+ if (slavePorts.find(name) == slavePorts.end()) {
+ std::cerr << "Slave Port " << name << " was not found!\n";
+ std::exit(EXIT_FAILURE);
+ }
+
+ return slavePorts.at(name);
+}
+
+SCMasterPort*
+Gem5SimControl::getMasterPort(const std::string& name)
+{
+ if (masterPorts.find(name) == masterPorts.end()) {
+ std::cerr << "Master Port " << name << " was not found!\n";
+ std::exit(EXIT_FAILURE);
+ }
+
+ return masterPorts.at(name);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Christian Menard
+ */
+
+#ifndef __SC_SIM_CONTROL_HH__
+#define __SC_SIM_CONTROL_HH__
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_logger.hh"
+#include "sc_module.hh"
+#include "sim/cxx_manager.hh"
+#include "sim/system.hh"
+#include "sim_control_if.hh"
+
+namespace Gem5SystemC
+{
+
+/**
+ * This is the central SystemC module that orchestrates the gem5 simulation.
+ *
+ * The module is responsible for loading the configuration file, setting up and
+ * maintaining the event queues, as well as starting and ending the simulation.
+ * While it is mandatory to have one instance of this class for running a gem5
+ * simulation in SystemC, it is not allowed to have multiple instances!
+ */
+class Gem5SimControl : public Module, public Gem5SimControlInterface
+{
+ protected:
+ CxxConfigManager* config_manager;
+ Gem5SystemC::Logger logger;
+
+ Tick simulationEnd;
+
+ /*
+ * Keep track of the slave and master ports that are created by gem5
+ * according to the config file.
+ */
+ std::map<const std::string, SCSlavePort*> slavePorts;
+ std::map<const std::string, SCMasterPort*> masterPorts;
+
+ /// Pointer to a previously created instance.
+ static Gem5SimControl* instance;
+
+ /** A callback that is called from the run thread before gem5 simulation is
+ * started.
+ *
+ * A derived class may use this to perform any additional initializations
+ * prior simulation.
+ */
+ virtual void beforeSimulate() {}
+
+ /** A callback that is called from the run thread after gem5 simulation
+ * completed.
+ *
+ * A derived class may use this to perform any additional tasks after gem5
+ * exits. For instance, a derived class could use this to call sc_stop().
+ */
+ virtual void afterSimulate() {}
+
+ public:
+ SC_HAS_PROCESS(Gem5SimControl);
+
+ /**
+ * Constructor.
+ *
+ * This class has a public constructor although the class is actually a
+ * singleton. The public constructor is required to ensure compatibility
+ * to external SystemC based tools. For the same reason, the constructor
+ * parameters are basic types (int, string).
+ *
+ * @param configFile location of the gem5 configuration file
+ * @param simulationEnd number of ticks to simulate
+ * @param gem5DebugFlags a space separated list of gem5 debug flags to be
+ * set, a prepended '-' clears the flag
+ */
+ Gem5SimControl(sc_core::sc_module_name name,
+ const std::string& configFile,
+ uint64_t simulationEnd,
+ const std::string& gem5DebugFlags);
+
+ void registerSlavePort(const std::string& name, SCSlavePort* port);
+ void registerMasterPort(const std::string& name, SCMasterPort* port);
+ SCSlavePort* getSlavePort(const std::string& name) override;
+ SCMasterPort* getMasterPort(const std::string& name) override;
+
+ void end_of_elaboration();
+
+ void run();
+};
+
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2017, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __SC_SIM_CONTROL_IF_HH__
+#define __SC_SIM_CONTROL_IF_HH__
+
+#include <systemc>
+
+namespace Gem5SystemC
+{
+
+// forward declerations
+class SCSlavePort;
+class SCMasterPort;
+
+class Gem5SimControlInterface : public sc_core::sc_interface
+{
+ public:
+ virtual SCSlavePort* getSlavePort(const std::string& name) = 0;
+ virtual SCMasterPort* getMasterPort(const std::string& name) = 0;
+};
+
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include "sc_slave_port.hh"
+#include "sim_control.hh"
+#include "slave_transactor.hh"
+
+namespace Gem5SystemC
+{
+
+Gem5SlaveTransactor::Gem5SlaveTransactor(sc_core::sc_module_name name,
+ const std::string& portName)
+ : sc_core::sc_module(name),
+ socket(portName.c_str()),
+ sim_control("sim_control"),
+ portName(portName)
+{
+ if (portName.empty()) {
+ SC_REPORT_ERROR(name, "No port name specified!\n");
+ }
+}
+
+void
+Gem5SlaveTransactor::before_end_of_elaboration()
+{
+ auto* port = sim_control->getSlavePort(portName);
+
+ port->bindToTransactor(this);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __GEM5_SLAVE_TRANSACTOR_HH__
+#define __GEM5_SLAVE_TRANSACTOR_HH__
+
+#include <tlm_utils/simple_initiator_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_slave_port.hh"
+#include "sim_control_if.hh"
+
+namespace Gem5SystemC
+{
+
+class Gem5SlaveTransactor : public sc_core::sc_module
+{
+ public:
+ // module interface
+ tlm_utils::simple_initiator_socket<SCSlavePort> socket;
+ sc_core::sc_port<Gem5SimControlInterface> sim_control;
+
+ private:
+ std::string portName;
+
+ public:
+ SC_HAS_PROCESS(Gem5SlaveTransactor);
+
+ Gem5SlaveTransactor(sc_core::sc_module_name name,
+ const std::string& portName);
+
+ void before_end_of_elaboration();
+};
+
+}
+
+#endif
projects / gem5.git / commitdiff