fixup: generated-verilog submodule for experimental Rocket support

FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS

diff --git a/.gitmodules b/.gitmodules
index d9db275422b7944e4e45741580edc313c1e80748..706bd180eaf8a44f204035519915c20f1be5f27c 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -19,3 +19,6 @@
 [submodule "litex/soc/cores/cpu/minerva/verilog"]
        path = litex/soc/cores/cpu/minerva/verilog
        url = http://github.com/enjoy-digital/minerva-verilog
+[submodule "litex/soc/cores/cpu/rocket/verilog"]
+       path = litex/soc/cores/cpu/rocket/verilog
+       url = https://github.com/gsomlo/rocket-litex-verilog

diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
new file mode 160000 (submodule)
index 0000000..bcb12b0
--- /dev/null
+++ b/litex/soc/cores/cpu/rocket/verilog
@@ -0,0 +1 @@
+Subproject commit bcb12b0233b050dddef8d9c69bbf590d10428647