This patch is adding new loads and stores defined by SME instructions.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_address): New parser.
(parse_sme_za_hv_tiles_operand_with_braces): New parser.
(parse_sme_za_array): New parser.
(output_operand_error_record): Print error details if
present.
(parse_operands): Support new operands.
* testsuite/gas/aarch64/sme-5-illegal.d: New test.
* testsuite/gas/aarch64/sme-5-illegal.l: New test.
* testsuite/gas/aarch64/sme-5-illegal.s: New test.
* testsuite/gas/aarch64/sme-5.d: New test.
* testsuite/gas/aarch64/sme-5.s: New test.
* testsuite/gas/aarch64/sme-6-illegal.d: New test.
* testsuite/gas/aarch64/sme-6-illegal.l: New test.
* testsuite/gas/aarch64/sme-6-illegal.s: New test.
* testsuite/gas/aarch64/sme-6.d: New test.
* testsuite/gas/aarch64/sme-6.s: New test.
* testsuite/gas/aarch64/sme-7-illegal.d: New test.
* testsuite/gas/aarch64/sme-7-illegal.l: New test.
* testsuite/gas/aarch64/sme-7-illegal.s: New test.
* testsuite/gas/aarch64/sme-7.d: New test.
* testsuite/gas/aarch64/sme-7.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands.
(enum aarch64_insn_class): Added sme_ldr and sme_str.
(AARCH64_OPDE_UNTIED_IMMS): New operand error kind.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter.
(aarch64_ins_sme_za_list): New inserter.
(aarch64_ins_sme_za_array): New inserter.
(aarch64_ins_sme_addr_ri_u4xvl): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added
ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor.
(aarch64_ext_sme_za_list): New extractor.
(aarch64_ext_sme_za_array): New extractor.
(aarch64_ext_sme_addr_ri_u4xvl): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added
ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl.
* aarch64-opc.c (operand_general_constraint_met_p):
(aarch64_match_operands_constraint): Handle sme_ldr, sme_str
and sme_misc.
(aarch64_print_operand): New operands supported.
* aarch64-tbl.h (OP_SVE_QUU): New qualifier.
(OP_SVE_QZU): New qualifier.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
return regno;
}
+
+static int
+parse_sme_za_hv_tiles_operand_with_braces (char **str,
+ enum sme_hv_slice *slice_indicator,
+ int *vector_select_register,
+ int *imm,
+ aarch64_opnd_qualifier_t *qualifier)
+{
+ int regno;
+
+ if (!skip_past_char (str, '{'))
+ {
+ set_syntax_error (_("expected '{'"));
+ return PARSE_FAIL;
+ }
+
+ regno = parse_sme_za_hv_tiles_operand (str, slice_indicator,
+ vector_select_register, imm,
+ qualifier);
+
+ if (regno == PARSE_FAIL)
+ return PARSE_FAIL;
+
+ if (!skip_past_char (str, '}'))
+ {
+ set_syntax_error (_("expected '}'"));
+ return PARSE_FAIL;
+ }
+
+ return regno;
+}
+
/* Parse list of up to eight 64-bit element tile names separated by commas in
SME's ZERO instruction:
return regno;
}
+/* Parse ZA array operand used in e.g. STR and LDR instruction.
+ Operand format:
+
+ ZA[<Wv>, <imm>]
+ ZA[<Wv>, #<imm>]
+
+ Function returns <Wv> or PARSE_FAIL.
+*/
+static int
+parse_sme_za_array (char **str, int *imm)
+{
+ char *p, *q;
+ int regno;
+ int64_t imm_value;
+
+ p = q = *str;
+ while (ISALPHA (*q))
+ q++;
+
+ if ((q - p != 2) || strncasecmp ("za", p, q - p) != 0)
+ {
+ set_syntax_error (_("expected ZA array"));
+ return PARSE_FAIL;
+ }
+
+ if (! parse_sme_za_hv_tiles_operand_index (&q, ®no, &imm_value))
+ return PARSE_FAIL;
+
+ if (imm_value < 0 || imm_value > 15)
+ {
+ set_syntax_error (_("offset out of range"));
+ return PARSE_FAIL;
+ }
+
+ *imm = imm_value;
+ *str = q;
+ return regno;
+}
+
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
}
break;
+ case AARCH64_OPDE_UNTIED_IMMS:
+ handler (_("operand %d must have the same immediate value "
+ "as operand 1 -- `%s'"),
+ detail->index + 1, str);
+ break;
+
case AARCH64_OPDE_UNTIED_OPERAND:
handler (_("operand %d must be the same register as operand 1 -- `%s'"),
- detail->index + 1, str);
+ detail->index + 1, str);
break;
case AARCH64_OPDE_OUT_OF_RANGE:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
+ case AARCH64_OPND_SME_ADDR_RI_U4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
goto failure;
}
goto regoff_addr;
-
+
case AARCH64_OPND_SVE_ADDR_RR:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
case AARCH64_OPND_SVE_ADDR_RR_LSL3:
+ case AARCH64_OPND_SVE_ADDR_RR_LSL4:
case AARCH64_OPND_SVE_ADDR_RX:
case AARCH64_OPND_SVE_ADDR_RX_LSL1:
case AARCH64_OPND_SVE_ADDR_RX_LSL2:
case AARCH64_OPND_SME_ZA_HV_idx_src:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
+ case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
{
- enum sme_hv_slice vector_indicator;
+ enum sme_hv_slice slice_indicator;
int vector_select_register;
int imm;
- val = parse_sme_za_hv_tiles_operand (&str, &vector_indicator,
- &vector_select_register,
- &imm,
- &qualifier);
+
+ if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr)
+ val = parse_sme_za_hv_tiles_operand_with_braces (&str,
+ &slice_indicator,
+ &vector_select_register,
+ &imm,
+ &qualifier);
+ else
+ val = parse_sme_za_hv_tiles_operand (&str, &slice_indicator,
+ &vector_select_register,
+ &imm,
+ &qualifier);
if (val == PARSE_FAIL)
goto failure;
info->za_tile_vector.regno = val;
info->za_tile_vector.index.regno = vector_select_register;
info->za_tile_vector.index.imm = imm;
- info->za_tile_vector.v = vector_indicator;
+ info->za_tile_vector.v = slice_indicator;
info->qualifier = qualifier;
break;
}
info->imm.value = val;
break;
+ case AARCH64_OPND_SME_ZA_array:
+ {
+ int imm;
+ val = parse_sme_za_array (&str, &imm);
+ if (val == PARSE_FAIL)
+ goto failure;
+ info->za_tile_vector.index.regno = val;
+ info->za_tile_vector.index.imm = imm;
+ break;
+ }
+
default:
as_fatal (_("unhandled operand code %d"), operands[i]);
}
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme-5-illegal.s
+#error_output: sme-5-illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {za0h.b\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0h.h\[w12,0\]},p0/z,\[x0,x1,lsl#2\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
--- /dev/null
+/* Scalable Matrix Extension (SME). */
+ld1b {za0h.b[w11, 0]}, p0/z, [x0]
+ld1h {za0h.h[w16, 0]}, p0/z, [x0]
+ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #3]
+ld1w {za3v.s[w15, 3]}, p7/z, [sp, lsl #2]
+ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #12]
+ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #2]
+ld1b {za1h.b[w12, 0]}, p0/z, [x0]
+ld1b {za1v.b[w12, 0]}, p0/z, [sp]
+ld1b {za1h.b[w12, 0]}, p0/z, [sp, x0]
+ld1b {za0v.b[w15, 16]}, p7/z, [x17]
+ld1b {za0h.b[w15, 16]}, p7/z, [sp]
+ld1b {za0v.b[w15, 16]}, p7/z, [sp, x17]
+ld1h {za2v.h[w12, 0]}, p0/z, [x0]
+ld1h {za2h.h[w12, 0]}, p0/z, [sp]
+ld1h {za2v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
+ld1h {za2h.h[w12, 0]}, p0/z, [sp, x0, lsl #1]
+ld1h {za1v.h[w15, 8]}, p7/z, [x17]
+ld1h {za1h.h[w15, 8]}, p7/z, [sp]
+ld1h {za1v.h[w15, 8]}, p7/z, [x0, x17, lsl #1]
+ld1h {za1h.h[w15, 8]}, p7/z, [sp, x17, lsl #1]
+ld1w {za4h.s[w12, 0]}, p0/z, [x0]
+ld1w {za4v.s[w12, 0]}, p0/z, [sp]
+ld1w {za4h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
+ld1w {za4v.s[w12, 0]}, p0/z, [sp, x0, lsl #2]
+ld1w {za3h.s[w15, 4]}, p7/z, [x17]
+ld1w {za3v.s[w15, 4]}, p7/z, [sp]
+ld1w {za3h.s[w15, 4]}, p7/z, [x0, x17, lsl #2]
+ld1w {za3v.s[w15, 4]}, p7/z, [sp, x17, lsl #2]
+ld1d {za8v.d[w12, 0]}, p0/z, [x0]
+ld1d {za8h.d[w12, 0]}, p0/z, [sp]
+ld1d {za8v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
+ld1d {za8h.d[w12, 0]}, p0/z, [sp, x0, lsl #3]
+ld1d {za7v.d[w15, 2]}, p7/z, [x17]
+ld1d {za7h.d[w15, 2]}, p7/z, [sp]
+ld1d {za7v.d[w15, 2]}, p7/z, [x0, x17, lsl #3]
+ld1d {za7h.d[w15, 2]}, p7/z, [sp, x17, lsl #3]
+ld1q {za16v.q[w12]}, p0/z, [x0]
+ld1q {za16h.q[w12]}, p0/z, [sp]
+ld1q {za16v.q[w12]}, p0/z, [x0, x0, lsl #4]
+ld1q {za16h.q[w12]}, p0/z, [sp, x0, lsl #4]
+ld1q {za15v.q[w15, 1]}, p7/z, [x17]
+ld1q {za15h.q[w15, 1]}, p7/z, [sp]
+ld1q {za15v.q[w15, 1]}, p7/z, [x0, x17, lsl #4]
+ld1q {za15h.q[w15, 1]}, p7/z, [sp, x17, lsl #4]
+/* Illegal operand 3 addressing modes. */
+ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1, lsl #1]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1, lsl #2]
+ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4]
+ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1]
+ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1]
--- /dev/null
+#name: SME extension (LD1x instructions)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: e01f0000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, xzr\]
+ 4: e01f03e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, xzr\]
+ 8: e00003e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, x0\]
+ c: e01f7e2f ld1b {za0h.b\[w15, 15\]}, p7/z, \[x17, xzr\]
+ 10: e01f7fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, xzr\]
+ 14: e0117fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, x17\]
+ 18: e05f0000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\]
+ 1c: e05f03e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\]
+ 20: e0400000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\]
+ 24: e04003e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\]
+ 28: e05f7e2f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\]
+ 2c: e05f7fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\]
+ 30: e0517c0f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\]
+ 34: e0517fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\]
+ 38: e09f0000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\]
+ 3c: e09f03e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\]
+ 40: e0800000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\]
+ 44: e08003e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\]
+ 48: e09f7e2f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\]
+ 4c: e09f7fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\]
+ 50: e0917c0f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\]
+ 54: e0917fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\]
+ 58: e0df0000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\]
+ 5c: e0df03e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\]
+ 60: e0c00000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\]
+ 64: e0c003e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\]
+ 68: e0df7e2f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\]
+ 6c: e0df7fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\]
+ 70: e0d17c0f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\]
+ 74: e0d17fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\]
+ 78: e1df0000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\]
+ 7c: e1df03e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\]
+ 80: e1c00000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\]
+ 84: e1c003e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\]
+ 88: e1df7e2f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\]
+ 8c: e1df7fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\]
+ 90: e1d17c0f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\]
+ 94: e1d17fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\]
+ 98: e01f8000 ld1b {za0v.b\[w12, 0\]}, p0/z, \[x0, xzr\]
+ 9c: e01f83e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, xzr\]
+ a0: e00083e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, x0\]
+ a4: e01ffe2f ld1b {za0v.b\[w15, 15\]}, p7/z, \[x17, xzr\]
+ a8: e01fffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, xzr\]
+ ac: e011ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x17\]
+ b0: e05f8000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\]
+ b4: e05f83e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\]
+ b8: e0408000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\]
+ bc: e04083e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\]
+ c0: e05ffe2f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\]
+ c4: e05fffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\]
+ c8: e051fc0f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\]
+ cc: e051ffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\]
+ d0: e09f8000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\]
+ d4: e09f83e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\]
+ d8: e0808000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\]
+ dc: e08083e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\]
+ e0: e09ffe2f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\]
+ e4: e09fffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\]
+ e8: e091fc0f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\]
+ ec: e091ffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\]
+ f0: e0df8000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\]
+ f4: e0df83e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\]
+ f8: e0c08000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\]
+ fc: e0c083e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\]
+ 100: e0dffe2f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\]
+ 104: e0dfffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\]
+ 108: e0d1fc0f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\]
+ 10c: e0d1ffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\]
+ 110: e1df8000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\]
+ 114: e1df83e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\]
+ 118: e1c08000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\]
+ 11c: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\]
+ 120: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\]
+ 124: e1dfffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\]
+ 128: e1d1fc0f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\]
+ 12c: e1d1ffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\]
+ 130: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\]
+ 134: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\]
+ 138: e000ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x0\]
+ 13c: e0010000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, x1\]
+ 140: e0410000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x1, lsl #1\]
+ 144: e0819c0f ld1w {za3v.s\[w12, 3\]}, p7/z, \[x0, x1, lsl #2\]
+ 148: e0c10000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x1, lsl #3\]
+ 14c: e1c18000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x1, lsl #4\]
--- /dev/null
+/* SME Extension (LD1x instructions). */
+ld1b {za0h.b[w12, 0]}, p0/z, [x0]
+ld1b {za0h.b[w12, 0]}, p0/z, [sp]
+ld1b {za0h.b[w12, 0]}, p0/z, [sp, x0]
+ld1b {za0h.b[w15, 15]}, p7/z, [x17]
+ld1b {za0h.b[w15, 15]}, p7/z, [sp]
+ld1b {za0h.b[w15, 15]}, p7/z, [sp, x17]
+
+ld1h {za0h.h[w12, 0]}, p0/z, [x0]
+ld1h {za0h.h[w12, 0]}, p0/z, [sp]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
+ld1h {za0h.h[w12, 0]}, p0/z, [sp, x0, lsl #1]
+ld1h {za1h.h[w15, 7]}, p7/z, [x17]
+ld1h {za1h.h[w15, 7]}, p7/z, [sp]
+ld1h {za1h.h[w15, 7]}, p7/z, [x0, x17, lsl #1]
+ld1h {za1h.h[w15, 7]}, p7/z, [sp, x17, lsl #1]
+
+ld1w {za0h.s[w12, 0]}, p0/z, [x0]
+ld1w {za0h.s[w12, 0]}, p0/z, [sp]
+ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
+ld1w {za0h.s[w12, 0]}, p0/z, [sp, x0, lsl #2]
+ld1w {za3h.s[w15, 3]}, p7/z, [x17]
+ld1w {za3h.s[w15, 3]}, p7/z, [sp]
+ld1w {za3h.s[w15, 3]}, p7/z, [x0, x17, lsl #2]
+ld1w {za3h.s[w15, 3]}, p7/z, [sp, x17, lsl #2]
+
+ld1d {za0h.d[w12, 0]}, p0/z, [x0]
+ld1d {za0h.d[w12, 0]}, p0/z, [sp]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
+ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #3]
+ld1d {za7h.d[w15, 1]}, p7/z, [x17]
+ld1d {za7h.d[w15, 1]}, p7/z, [sp]
+ld1d {za7h.d[w15, 1]}, p7/z, [x0, x17, lsl #3]
+ld1d {za7h.d[w15, 1]}, p7/z, [sp, x17, lsl #3]
+
+ld1q {za0h.q[w12, 0]}, p0/z, [x0]
+ld1q {za0h.q[w12, 0]}, p0/z, [sp]
+ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
+ld1q {za0h.q[w12, 0]}, p0/z, [sp, x0, lsl #4]
+ld1q {za15h.q[w15, 0]}, p7/z, [x17]
+ld1q {za15h.q[w15, 0]}, p7/z, [sp]
+ld1q {za15h.q[w15, 0]}, p7/z, [x0, x17, lsl #4]
+ld1q {za15h.q[w15, 0]}, p7/z, [sp, x17, lsl #4]
+
+ld1b {za0v.b[w12, 0]}, p0/z, [x0]
+ld1b {za0v.b[w12, 0]}, p0/z, [sp]
+ld1b {za0v.b[w12, 0]}, p0/z, [sp, x0]
+ld1b {za0v.b[w15, 15]}, p7/z, [x17]
+ld1b {za0v.b[w15, 15]}, p7/z, [sp]
+ld1b {za0v.b[w15, 15]}, p7/z, [sp, x17]
+
+ld1h {za0v.h[w12, 0]}, p0/z, [x0]
+ld1h {za0v.h[w12, 0]}, p0/z, [sp]
+ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
+ld1h {za0v.h[w12, 0]}, p0/z, [sp, x0, lsl #1]
+ld1h {za1v.h[w15, 7]}, p7/z, [x17]
+ld1h {za1v.h[w15, 7]}, p7/z, [sp]
+ld1h {za1v.h[w15, 7]}, p7/z, [x0, x17, lsl #1]
+ld1h {za1v.h[w15, 7]}, p7/z, [sp, x17, lsl #1]
+
+ld1w {za0v.s[w12, 0]}, p0/z, [x0]
+ld1w {za0v.s[w12, 0]}, p0/z, [sp]
+ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
+ld1w {za0v.s[w12, 0]}, p0/z, [sp, x0, lsl #2]
+ld1w {za3v.s[w15, 3]}, p7/z, [x17]
+ld1w {za3v.s[w15, 3]}, p7/z, [sp]
+ld1w {za3v.s[w15, 3]}, p7/z, [x0, x17, lsl #2]
+ld1w {za3v.s[w15, 3]}, p7/z, [sp, x17, lsl #2]
+
+ld1d {za0v.d[w12, 0]}, p0/z, [x0]
+ld1d {za0v.d[w12, 0]}, p0/z, [sp]
+ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
+ld1d {za0v.d[w12, 0]}, p0/z, [sp, x0, lsl #3]
+ld1d {za7v.d[w15, 1]}, p7/z, [x17]
+ld1d {za7v.d[w15, 1]}, p7/z, [sp]
+ld1d {za7v.d[w15, 1]}, p7/z, [x0, x17, lsl #3]
+ld1d {za7v.d[w15, 1]}, p7/z, [sp, x17, lsl #3]
+
+ld1q {za0v.q[w12, 0]}, p0/z, [x0]
+ld1q {za0v.q[w12, 0]}, p0/z, [sp]
+ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
+ld1q {za0v.q[w12, 0]}, p0/z, [sp, x0, lsl #4]
+ld1q {za15v.q[w15, 0]}, p7/z, [x17]
+ld1q {za15v.q[w15, 0]}, p7/z, [sp]
+ld1q {za15v.q[w15, 0]}, p7/z, [x0, x17, lsl #4]
+ld1q {za15v.q[w15, 0]}, p7/z, [sp, x17, lsl #4]
+
+/* Register aliases. */
+foo .req za0v
+bar .req w15
+
+ld1q {foo.q[w12, #0]}, p0/z, [sp, x0, lsl #4]
+ld1q {za15v.q[bar, #0]}, p7/z, [x17]
+
+/* Optional LSL operator. */
+ld1b {za0v.b[w15, 15]}, p7/z, [sp, x0, lsl #0]
+ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1]
+ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1]
+ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1]
+ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1]
+ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme-6-illegal.s
+#error_output: sme-6-illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
+[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
+[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]'
--- /dev/null
+/* Scalable Matrix Extension (SME). */
+
+st1b {za0h.b[w11, 0]}, p0, [x0]
+st1h {za0h.h[w16, 0]}, p0, [x0]
+st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #3]
+st1w {za3v.s[w15, 3]}, p7, [sp, lsl #2]
+st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #12]
+st1q {za0v.q[w12]}, p0, [x0, x0, lsl #2]
+st1b {za1h.b[w12, 0]}, p0, [x0]
+st1b {za1v.b[w12, 0]}, p0, [sp]
+st1b {za1h.b[w12, 0]}, p0, [sp, x0]
+st1b {za0v.b[w15, 16]}, p7, [x17]
+st1b {za0h.b[w15, 16]}, p7, [sp]
+st1b {za0v.b[w15, 16]}, p7, [sp, x17]
+st1h {za2v.h[w12, 0]}, p0, [x0]
+st1h {za2h.h[w12, 0]}, p0, [sp]
+st1h {za2v.h[w12, 0]}, p0, [x0, x0, lsl #1]
+st1h {za2h.h[w12, 0]}, p0, [sp, x0, lsl #1]
+st1h {za1v.h[w15, 8]}, p7, [x17]
+st1h {za1h.h[w15, 8]}, p7, [sp]
+st1h {za1v.h[w15, 8]}, p7, [x0, x17, lsl #1]
+st1h {za1h.h[w15, 8]}, p7, [sp, x17, lsl #1]
+st1w {za4h.s[w12, 0]}, p0, [x0]
+st1w {za4v.s[w12, 0]}, p0, [sp]
+st1w {za4h.s[w12, 0]}, p0, [x0, x0, lsl #2]
+st1w {za4v.s[w12, 0]}, p0, [sp, x0, lsl #2]
+st1w {za3h.s[w15, 4]}, p7, [x17]
+st1w {za3v.s[w15, 4]}, p7, [sp]
+st1w {za3h.s[w15, 4]}, p7, [x0, x17, lsl #2]
+st1w {za3v.s[w15, 4]}, p7, [sp, x17, lsl #2]
+st1d {za8v.d[w12, 0]}, p0, [x0]
+st1d {za8h.d[w12, 0]}, p0, [sp]
+st1d {za8v.d[w12, 0]}, p0, [x0, x0, lsl #3]
+st1d {za8h.d[w12, 0]}, p0, [sp, x0, lsl #3]
+st1d {za7v.d[w15, 2]}, p7, [x17]
+st1d {za7h.d[w15, 2]}, p7, [sp]
+st1d {za7v.d[w15, 2]}, p7, [x0, x17, lsl #3]
+st1d {za7h.d[w15, 2]}, p7, [sp, x17, lsl #3]
+st1q {za16v.q[w12]}, p0, [x0]
+st1q {za16h.q[w12]}, p0, [sp]
+st1q {za16v.q[w12]}, p0, [x0, x0, lsl #4]
+st1q {za16h.q[w12]}, p0, [sp, x0, lsl #4]
+st1q {za15v.q[w15, 1]}, p7, [x17]
+st1q {za15h.q[w15, 1]}, p7, [sp]
+st1q {za15v.q[w15, 1]}, p7, [x0, x17, lsl #4]
+st1q {za15h.q[w15, 1]}, p7, [sp, x17, lsl #4]
--- /dev/null
+#name: SME extension (ST1x instructions)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: e03f0000 st1b {za0h.b\[w12, 0\]}, p0, \[x0, xzr\]
+ 4: e03f03e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, xzr\]
+ 8: e02003e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, x0\]
+ c: e03f7e2f st1b {za0h.b\[w15, 15\]}, p7, \[x17, xzr\]
+ 10: e03f7fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, xzr\]
+ 14: e0317fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, x17\]
+ 18: e07f0000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\]
+ 1c: e07f03e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\]
+ 20: e0600000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\]
+ 24: e06003e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\]
+ 28: e07f7e2f st1h {za1h.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\]
+ 2c: e07f7fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\]
+ 30: e0717c0f st1h {za1h.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\]
+ 34: e0717fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\]
+ 38: e0bf0000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\]
+ 3c: e0bf03e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\]
+ 40: e0a00000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\]
+ 44: e0a003e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\]
+ 48: e0bf7e2f st1w {za3h.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\]
+ 4c: e0bf7fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\]
+ 50: e0b17c0f st1w {za3h.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\]
+ 54: e0b17fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\]
+ 58: e0ff0000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\]
+ 5c: e0ff03e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\]
+ 60: e0e00000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\]
+ 64: e0e003e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\]
+ 68: e0ff7e2f st1d {za7h.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\]
+ 6c: e0ff7fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\]
+ 70: e0f17c0f st1d {za7h.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\]
+ 74: e0f17fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\]
+ 78: e1ff0000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\]
+ 7c: e1ff03e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\]
+ 80: e1e00000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\]
+ 84: e1e003e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\]
+ 88: e1ff7e2f st1q {za15h.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\]
+ 8c: e1ff7fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\]
+ 90: e1f17c0f st1q {za15h.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\]
+ 94: e1f17fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\]
+ 98: e03f8000 st1b {za0v.b\[w12, 0\]}, p0, \[x0, xzr\]
+ 9c: e03f83e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, xzr\]
+ a0: e02083e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, x0\]
+ a4: e03ffe2f st1b {za0v.b\[w15, 15\]}, p7, \[x17, xzr\]
+ a8: e03fffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, xzr\]
+ ac: e031ffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, x17\]
+ b0: e07f8000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\]
+ b4: e07f83e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\]
+ b8: e0608000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\]
+ bc: e06083e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\]
+ c0: e07ffe2f st1h {za1v.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\]
+ c4: e07fffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\]
+ c8: e071fc0f st1h {za1v.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\]
+ cc: e071ffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\]
+ d0: e0bf8000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\]
+ d4: e0bf83e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\]
+ d8: e0a08000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\]
+ dc: e0a083e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\]
+ e0: e0bffe2f st1w {za3v.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\]
+ e4: e0bfffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\]
+ e8: e0b1fc0f st1w {za3v.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\]
+ ec: e0b1ffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\]
+ f0: e0ff8000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\]
+ f4: e0ff83e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\]
+ f8: e0e08000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\]
+ fc: e0e083e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\]
+ 100: e0fffe2f st1d {za7v.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\]
+ 104: e0ffffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\]
+ 108: e0f1fc0f st1d {za7v.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\]
+ 10c: e0f1ffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\]
+ 110: e1ff8000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\]
+ 114: e1ff83e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\]
+ 118: e1e08000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\]
+ 11c: e1e083e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\]
+ 120: e1fffe2f st1q {za15v.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\]
+ 124: e1ffffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\]
+ 128: e1f1fc0f st1q {za15v.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\]
+ 12c: e1f1ffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\]
--- /dev/null
+/* SME Extension (ST1x instructions). */
+st1b {za0h.b[w12, 0]}, p0, [x0]
+st1b {za0h.b[w12, 0]}, p0, [sp]
+st1b {za0h.b[w12, 0]}, p0, [sp, x0]
+st1b {za0h.b[w15, 15]}, p7, [x17]
+st1b {za0h.b[w15, 15]}, p7, [sp]
+st1b {za0h.b[w15, 15]}, p7, [sp, x17]
+
+st1h {za0h.h[w12, 0]}, p0, [x0]
+st1h {za0h.h[w12, 0]}, p0, [sp]
+st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
+st1h {za0h.h[w12, 0]}, p0, [sp, x0, lsl #1]
+st1h {za1h.h[w15, 7]}, p7, [x17]
+st1h {za1h.h[w15, 7]}, p7, [sp]
+st1h {za1h.h[w15, 7]}, p7, [x0, x17, lsl #1]
+st1h {za1h.h[w15, 7]}, p7, [sp, x17, lsl #1]
+
+st1w {za0h.s[w12, 0]}, p0, [x0]
+st1w {za0h.s[w12, 0]}, p0, [sp]
+st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
+st1w {za0h.s[w12, 0]}, p0, [sp, x0, lsl #2]
+st1w {za3h.s[w15, 3]}, p7, [x17]
+st1w {za3h.s[w15, 3]}, p7, [sp]
+st1w {za3h.s[w15, 3]}, p7, [x0, x17, lsl #2]
+st1w {za3h.s[w15, 3]}, p7, [sp, x17, lsl #2]
+
+st1d {za0h.d[w12, 0]}, p0, [x0]
+st1d {za0h.d[w12, 0]}, p0, [sp]
+st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
+st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #3]
+st1d {za7h.d[w15, 1]}, p7, [x17]
+st1d {za7h.d[w15, 1]}, p7, [sp]
+st1d {za7h.d[w15, 1]}, p7, [x0, x17, lsl #3]
+st1d {za7h.d[w15, 1]}, p7, [sp, x17, lsl #3]
+
+st1q {za0h.q[w12, 0]}, p0, [x0]
+st1q {za0h.q[w12, 0]}, p0, [sp]
+st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
+st1q {za0h.q[w12, 0]}, p0, [sp, x0, lsl #4]
+st1q {za15h.q[w15, 0]}, p7, [x17]
+st1q {za15h.q[w15, 0]}, p7, [sp]
+st1q {za15h.q[w15, 0]}, p7, [x0, x17, lsl #4]
+st1q {za15h.q[w15, 0]}, p7, [sp, x17, lsl #4]
+
+st1b {za0v.b[w12, 0]}, p0, [x0]
+st1b {za0v.b[w12, 0]}, p0, [sp]
+st1b {za0v.b[w12, 0]}, p0, [sp, x0]
+st1b {za0v.b[w15, 15]}, p7, [x17]
+st1b {za0v.b[w15, 15]}, p7, [sp]
+st1b {za0v.b[w15, 15]}, p7, [sp, x17]
+
+st1h {za0v.h[w12, 0]}, p0, [x0]
+st1h {za0v.h[w12, 0]}, p0, [sp]
+st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
+st1h {za0v.h[w12, 0]}, p0, [sp, x0, lsl #1]
+st1h {za1v.h[w15, 7]}, p7, [x17]
+st1h {za1v.h[w15, 7]}, p7, [sp]
+st1h {za1v.h[w15, 7]}, p7, [x0, x17, lsl #1]
+st1h {za1v.h[w15, 7]}, p7, [sp, x17, lsl #1]
+
+st1w {za0v.s[w12, 0]}, p0, [x0]
+st1w {za0v.s[w12, 0]}, p0, [sp]
+st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
+st1w {za0v.s[w12, 0]}, p0, [sp, x0, lsl #2]
+st1w {za3v.s[w15, 3]}, p7, [x17]
+st1w {za3v.s[w15, 3]}, p7, [sp]
+st1w {za3v.s[w15, 3]}, p7, [x0, x17, lsl #2]
+st1w {za3v.s[w15, 3]}, p7, [sp, x17, lsl #2]
+
+st1d {za0v.d[w12, 0]}, p0, [x0]
+st1d {za0v.d[w12, 0]}, p0, [sp]
+st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
+st1d {za0v.d[w12, 0]}, p0, [sp, x0, lsl #3]
+st1d {za7v.d[w15, 1]}, p7, [x17]
+st1d {za7v.d[w15, 1]}, p7, [sp]
+st1d {za7v.d[w15, 1]}, p7, [x0, x17, lsl #3]
+st1d {za7v.d[w15, 1]}, p7, [sp, x17, lsl #3]
+
+st1q {za0v.q[w12, 0]}, p0, [x0]
+st1q {za0v.q[w12, 0]}, p0, [sp]
+st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
+st1q {za0v.q[w12, 0]}, p0, [sp, x0, lsl #4]
+st1q {za15v.q[w15, 0]}, p7, [x17]
+st1q {za15v.q[w15, 0]}, p7, [sp]
+st1q {za15v.q[w15, 0]}, p7, [x0, x17, lsl #4]
+st1q {za15v.q[w15, 0]}, p7, [sp, x17, lsl #4]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme-7-illegal.s
+#error_output: sme-7-illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]'
+[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w15,15\],\[sp,#15,mul#4\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,13\],\[x17,#23,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,13\],\[x17,#23,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]'
+[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]'
+[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]'
--- /dev/null
+/* Scalable Matrix Extension (SME). */
+
+/* Load vector to ZA array. */
+ldr za[w11, 0], [x0]
+ldr za[w12, 1], [sp, x0]
+ldr za[w12, 0], [sp, #1, mul vl]
+ldr za[w13, 9], [x17, #19, mul vl]
+ldr za[w13, 21], [x17, #21, mul vl]
+ldr za[w15, 32], [x17, #15, mul vl]
+ldr za[w16, 15], [sp, #15, mul vl]
+ldr za[w12, 0], [x0, #0, mul #1]
+ldr za[w13, 0], [sp, #0, mul #2]
+ldr za[w14, 9], [x17, #9, mul #3]
+ldr za[w15, 15], [sp, #15, mul #4]
+
+/* Store vector from ZA array. */
+str za[w11, 0], [x0]
+str za[w12, 1], [sp, x0]
+str za[w12, 0], [sp, #1, mul vl]
+str za[w13, 9], [x17, #19, mul vl]
+str za[w13, 21], [x17, #21, mul vl]
+str za[w15, 32], [x17, #15, mul vl]
+str za[w16, 15], [sp, #15, mul vl]
+str za[w12, 0], [x0, #0, mul #1]
+str za[w13, 0], [sp, #0, mul #2]
+str za[w14, 9], [x17, #9, mul #3]
+str za[w15, 15], [sp, #15, mul #4]
+
+/* Operands indexes are tied. */
+ldr za[w13, 13], [x17, #23, mul vl]
+str za[w13, 13], [x17, #23, mul vl]
+ldr za[w13, 23], [x17, #13, mul vl]
+str za[w13, 23], [x17, #13, mul vl]
+ldr za[w13, 16], [x17, #16, mul vl]
+str za[w13, 16], [x17, #16, mul vl]
+ldr za[w13, -1], [x17, #1, mul vl]
+str za[w13, -1], [x17, #1, mul vl]
+ldr za[w13, 1], [x17, #-1, mul vl]
+str za[w13, 1], [x17, #-1, mul vl]
--- /dev/null
+#name: SME extension (LDR and STR instructions)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: e1000000 ldr za\[w12, 0\], \[x0\]
+ 4: e10003e0 ldr za\[w12, 0\], \[sp\]
+ 8: e1000000 ldr za\[w12, 0\], \[x0\]
+ c: e10003e0 ldr za\[w12, 0\], \[sp\]
+ 10: e1006220 ldr za\[w15, 0\], \[x17\]
+ 14: e1002229 ldr za\[w13, 9\], \[x17, #9, mul vl\]
+ 18: e100622f ldr za\[w15, 15\], \[x17, #15, mul vl\]
+ 1c: e10063ef ldr za\[w15, 15\], \[sp, #15, mul vl\]
+ 20: e1200000 str za\[w12, 0\], \[x0\]
+ 24: e12003e0 str za\[w12, 0\], \[sp\]
+ 28: e1200000 str za\[w12, 0\], \[x0\]
+ 2c: e12003e0 str za\[w12, 0\], \[sp\]
+ 30: e1206220 str za\[w15, 0\], \[x17\]
+ 34: e1202229 str za\[w13, 9\], \[x17, #9, mul vl\]
+ 38: e120622f str za\[w15, 15\], \[x17, #15, mul vl\]
+ 3c: e12063ef str za\[w15, 15\], \[sp, #15, mul vl\]
+ 40: e10003e0 ldr za\[w12, 0\], \[sp\]
+ 44: e1206220 str za\[w15, 0\], \[x17\]
--- /dev/null
+/* SME Extension (LDR and STR instructions). */
+/* Load vector to ZA array. */
+ldr za[w12, 0], [x0]
+ldr za[w12, 0], [sp]
+ldr za[w12, 0], [x0, #0, mul vl]
+ldr za[w12, 0], [sp, #0, mul vl]
+ldr za[w15, 0], [x17]
+ldr za[w13, 9], [x17, #9, mul vl]
+ldr za[w15, 15], [x17, #15, mul vl]
+ldr za[w15, 15], [sp, #15, mul vl]
+
+/* Store vector from ZA array. */
+str za[w12, 0], [x0]
+str za[w12, 0], [sp]
+str za[w12, 0], [x0, #0, mul vl]
+str za[w12, 0], [sp, #0, mul vl]
+str za[w15, 0], [x17]
+str za[w13, 9], [x17, #9, mul vl]
+str za[w15, 15], [x17, #15, mul vl]
+str za[w15, 15], [sp, #15, mul vl]
+
+/* Register aliases. */
+foo .req w12
+bar .req w15
+
+ldr za[foo, 0], [sp, #0, mul vl]
+str za[bar, 0], [x17]
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
-
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
+ AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */
AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
+ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
+ AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
+ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
pcreladdr,
ic_system,
sme_misc,
+ sme_ldr,
+ sme_str,
sve_cpy,
sve_index,
sve_limm,
No syntax error, but the operands are not a valid combination, e.g.
FMOV D0,S0
+ AARCH64_OPDE_UNTIED_IMMS
+ The asm failed to use the same immediate for a destination operand
+ and a tied source operand.
+
AARCH64_OPDE_UNTIED_OPERAND
The asm failed to use the same register for a destination operand
and a tied source operand.
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
+ AARCH64_OPDE_UNTIED_IMMS,
AARCH64_OPDE_UNTIED_OPERAND,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
case 29:
case 30:
case 31:
- case 166:
case 167:
case 168:
case 169:
case 173:
case 174:
case 175:
- case 190:
+ case 176:
case 191:
case 192:
case 193:
case 196:
case 197:
case 198:
- case 204:
- case 207:
- case 209:
+ case 199:
+ case 205:
+ case 208:
case 210:
- case 213:
+ case 211:
+ case 214:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 216:
+ case 220:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 82:
case 83:
case 84:
- case 163:
- case 165:
- case 182:
+ case 164:
+ case 166:
case 183:
case 184:
case 185:
case 187:
case 188:
case 189:
- case 214:
+ case 190:
case 215:
+ case 219:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
case 48:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 52:
- case 153:
+ case 154:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 70:
- case 161:
+ case 162:
return aarch64_ins_limm (self, info, code, inst, errors);
case 71:
return aarch64_ins_aimm (self, info, code, inst, errors);
return aarch64_ins_fbits (self, info, code, inst, errors);
case 75:
case 76:
- case 158:
+ case 159:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 77:
- case 157:
- case 159:
+ case 158:
+ case 160:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 78:
case 79:
case 133:
case 134:
case 135:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 136:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 137:
case 138:
case 139:
case 141:
case 142:
case 143:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 144:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 145:
case 146:
case 147:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 148:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 149:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 150:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 151:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 152:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 153:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 154:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 155:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 156:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 157:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 160:
+ case 161:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 162:
+ case 163:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 164:
+ case 165:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 176:
case 177:
case 178:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 179:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 180:
case 181:
+ case 182:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 199:
case 200:
case 201:
case 202:
case 203:
+ case 204:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 205:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 206:
- case 208:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 207:
+ case 209:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- case 211:
case 212:
+ case 213:
+ case 216:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 217:
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
+ case 218:
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
default: assert (0); abort ();
}
}
return true;
}
+/* Encode in SME instruction ZERO list of up to eight 64-bit element tile names
+ separated by commas, encoded in the "imm8" field.
+
+ For programmer convenience an assembler must also accept the names of
+ 32-bit, 16-bit and 8-bit element tiles which are converted into the
+ corresponding set of 64-bit element tiles.
+*/
+bool
+aarch64_ins_sme_za_list (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int fld_mask = info->imm.value;
+ insert_field (self->fields[0], code, fld_mask, 0);
+ return true;
+}
+
+bool
+aarch64_ins_sme_za_array (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int regno = info->za_tile_vector.index.regno - 12;
+ int imm = info->za_tile_vector.index.imm;
+ insert_field (self->fields[0], code, regno, 0);
+ insert_field (self->fields[1], code, imm, 0);
+ return true;
+}
+
+bool
+aarch64_ins_sme_addr_ri_u4xvl (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int regno = info->addr.base_regno;
+ int imm = info->addr.offset.imm;
+ insert_field (self->fields[0], code, regno, 0);
+ insert_field (self->fields[1], code, imm, 0);
+ return true;
+}
+
/* Miscellaneous encoding functions. */
/* Encode size[0], i.e. bit 22, for
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles);
+AARCH64_DECL_OPD_INSERTER (ins_sme_za_list);
+AARCH64_DECL_OPD_INSERTER (ins_sme_za_array);
+AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
{
if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100000x00xxxxxxxxxxxxxxxx0xxxx
- smopa. */
- return 2360;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100000000xxxxxxxxxxxxxxxx0xxxx
+ ld1b. */
+ return 2381;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000100xxxxxxxxxxxxxxxx0xxxx
+ smopa. */
+ return 2360;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000100xxxxxxxxxxxxxxxx0xxxx
+ ld1w. */
+ return 2383;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100000x10xxxxxxxxxxxxxxxx0xxxx
- smopa. */
- return 2361;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100000010xxxxxxxxxxxxxxxx0xxxx
+ ld1h. */
+ return 2382;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000110xxxxxxxxxxxxxxxx0xxxx
+ smopa. */
+ return 2361;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000110xxxxxxxxxxxxxxxx0xxxx
+ ld1d. */
+ return 2384;
+ }
+ }
}
}
else
{
if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000x01xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2364;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00000001xxxxxxxxxxxxxxxx0xxxx
+ st1b. */
+ return 2391;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000101xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2364;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000101xxxxxxxxxxxxxxxx0xxxx
+ st1w. */
+ return 2393;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000x11xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2365;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00000011xxxxxxxxxxxxxxxx0xxxx
+ st1h. */
+ return 2392;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000111xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2365;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000111xxxxxxxxxxxxxxxx0xxxx
+ st1d. */
+ return 2394;
+ }
+ }
}
}
else
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001x00xxxxxxxxxxxxxxxx0xxxx
- bfmopa. */
- return 2352;
+ xxx00001000xxxxxxxxxxxxxxxx0xxxx
+ ldr. */
+ return 2401;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001x00xxxxxxxxxxxxxxxx0xxxx
- usmopa. */
- return 2372;
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001100xxxxxxxxxxxxxxxx0xxxx
+ bfmopa. */
+ return 2352;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001100xxxxxxxxxxxxxxxx0xxxx
+ usmopa. */
+ return 2372;
+ }
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001x10xxxxxxxxxxxxxxxx0xxxx
- usmopa. */
- return 2373;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001x10xxxxxxxxxxxxxxxx0xxxx
+ usmopa. */
+ return 2373;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001x10xxxxxxxxxxxxxxxx0xxxx
+ ld1q. */
+ return 2385;
+ }
}
}
else
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001x01xxxxxxxxxxxxxxxx0xxxx
- fmopa. */
- return 2356;
+ xxx00001001xxxxxxxxxxxxxxxx0xxxx
+ str. */
+ return 2402;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001x01xxxxxxxxxxxxxxxx0xxxx
- umopa. */
- return 2368;
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001101xxxxxxxxxxxxxxxx0xxxx
+ fmopa. */
+ return 2356;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001101xxxxxxxxxxxxxxxx0xxxx
+ umopa. */
+ return 2368;
+ }
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001x11xxxxxxxxxxxxxxxx0xxxx
- umopa. */
- return 2369;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001x11xxxxxxxxxxxxxxxx0xxxx
+ umopa. */
+ return 2369;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001x11xxxxxxxxxxxxxxxx0xxxx
+ st1q. */
+ return 2395;
+ }
}
}
}
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2421;
+ return 2443;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2429;
+ return 2451;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2425;
+ return 2447;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2432;
+ return 2454;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2422;
+ return 2444;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2430;
+ return 2452;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2426;
+ return 2448;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2433;
+ return 2455;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2424;
+ return 2446;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2431;
+ return 2453;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2428;
+ return 2450;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2423;
+ return 2445;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2427;
+ return 2449;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2419;
+ return 2441;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2420;
+ return 2442;
}
}
else
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2418;
+ return 2440;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2438;
+ return 2460;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2439;
+ return 2461;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2437;
+ return 2459;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2466;
+ return 2488;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2442;
+ return 2464;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2443;
+ return 2465;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2463;
+ return 2485;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2470;
+ return 2492;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2469;
+ return 2491;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2462;
+ return 2484;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2468;
+ return 2490;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2467;
+ return 2489;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2446;
+ return 2468;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2447;
+ return 2469;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2440;
+ return 2462;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2464;
+ return 2486;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2441;
+ return 2463;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2450;
+ return 2472;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2452;
+ return 2474;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2454;
+ return 2476;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2451;
+ return 2473;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2453;
+ return 2475;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2455;
+ return 2477;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2434;
+ return 2456;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2436;
+ return 2458;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2435;
+ return 2457;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2444;
+ return 2466;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2445;
+ return 2467;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2448;
+ return 2470;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2449;
+ return 2471;
}
}
}
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2465;
+ return 2487;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2456;
+ return 2478;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2382;
+ return 2404;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2458;
+ return 2480;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2459;
+ return 2481;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2389;
+ return 2411;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2391;
+ return 2413;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2393;
+ return 2415;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2394;
+ return 2416;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2387;
+ return 2409;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2396;
+ return 2418;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2395;
+ return 2417;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2400;
+ return 2422;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2397;
+ return 2419;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2381;
+ return 2403;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2457;
+ return 2479;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2473;
+ return 2495;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2471;
+ return 2493;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2478;
+ return 2500;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2477;
+ return 2499;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2474;
+ return 2496;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2475;
+ return 2497;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2392;
+ return 2414;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2385;
+ return 2407;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2398;
+ return 2420;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2388;
+ return 2410;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2401;
+ return 2423;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2386;
+ return 2408;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2399;
+ return 2421;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2390;
+ return 2412;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2404;
+ return 2426;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2408;
+ return 2430;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2405;
+ return 2427;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2409;
+ return 2431;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2402;
+ return 2424;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2406;
+ return 2428;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2403;
+ return 2425;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2407;
+ return 2429;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2410;
+ return 2432;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2414;
+ return 2436;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2411;
+ return 2433;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2415;
+ return 2437;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2412;
+ return 2434;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2416;
+ return 2438;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2413;
+ return 2435;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2417;
+ return 2439;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2384;
+ return 2406;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2383;
+ return 2405;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2461;
+ return 2483;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2460;
+ return 2482;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2472;
+ return 2494;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2480;
+ return 2502;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2479;
+ return 2501;
}
}
}
case 2379: return NULL; /* mova --> NULL. */
case 2376: value = 2378; break; /* mov --> mova. */
case 2378: return NULL; /* mova --> NULL. */
+ case 2381: value = 2386; break; /* ld1b --> ld1b. */
+ case 2386: return NULL; /* ld1b --> NULL. */
+ case 2383: value = 2388; break; /* ld1w --> ld1w. */
+ case 2388: return NULL; /* ld1w --> NULL. */
+ case 2382: value = 2387; break; /* ld1h --> ld1h. */
+ case 2387: return NULL; /* ld1h --> NULL. */
+ case 2384: value = 2389; break; /* ld1d --> ld1d. */
+ case 2389: return NULL; /* ld1d --> NULL. */
+ case 2391: value = 2396; break; /* st1b --> st1b. */
+ case 2396: return NULL; /* st1b --> NULL. */
+ case 2393: value = 2398; break; /* st1w --> st1w. */
+ case 2398: return NULL; /* st1w --> NULL. */
+ case 2392: value = 2397; break; /* st1h --> st1h. */
+ case 2397: return NULL; /* st1h --> NULL. */
+ case 2394: value = 2399; break; /* st1d --> st1d. */
+ case 2399: return NULL; /* st1d --> NULL. */
+ case 2385: value = 2390; break; /* ld1q --> ld1q. */
+ case 2390: return NULL; /* ld1q --> NULL. */
+ case 2395: value = 2400; break; /* st1q --> st1q. */
+ case 2400: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
case 19: return NULL; /* addg --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2476; break; /* fcvt --> bfcvt. */
- case 2476: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2498; break; /* fcvt --> bfcvt. */
+ case 2498: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 29:
case 30:
case 31:
- case 166:
case 167:
case 168:
case 169:
case 173:
case 174:
case 175:
- case 190:
+ case 176:
case 191:
case 192:
case 193:
case 196:
case 197:
case 198:
- case 204:
- case 207:
- case 209:
+ case 199:
+ case 205:
+ case 208:
case 210:
- case 213:
+ case 211:
+ case 214:
return aarch64_ext_regno (self, info, code, inst, errors);
case 10:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 216:
+ case 220:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 82:
case 83:
case 84:
- case 163:
- case 165:
- case 182:
+ case 164:
+ case 166:
case 183:
case 184:
case 185:
case 187:
case 188:
case 189:
- case 214:
+ case 190:
case 215:
+ case 219:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
case 49:
return aarch64_ext_shll_imm (self, info, code, inst, errors);
case 52:
- case 153:
+ case 154:
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 70:
- case 161:
+ case 162:
return aarch64_ext_limm (self, info, code, inst, errors);
case 71:
return aarch64_ext_aimm (self, info, code, inst, errors);
return aarch64_ext_fbits (self, info, code, inst, errors);
case 75:
case 76:
- case 158:
+ case 159:
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 77:
- case 157:
- case 159:
+ case 158:
+ case 160:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 78:
case 79:
case 133:
case 134:
case 135:
- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 136:
+ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 137:
case 138:
case 139:
case 141:
case 142:
case 143:
- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 144:
+ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 145:
case 146:
case 147:
- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 148:
- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 149:
- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
case 150:
- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 151:
- return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 152:
+ return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ case 153:
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
- case 154:
- return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 155:
- return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 156:
+ return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ case 157:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 160:
+ case 161:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 162:
+ case 163:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 164:
+ case 165:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
- case 176:
case 177:
case 178:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 179:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 180:
case 181:
+ case 182:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 199:
case 200:
case 201:
case 202:
case 203:
+ case 204:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 205:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 206:
- case 208:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 207:
+ case 209:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
- case 211:
case 212:
+ case 213:
+ case 216:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 217:
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
+ case 218:
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
default: assert (0); abort ();
}
}
return true;
}
+/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names
+ separated by commas, encoded in the "imm8" field.
+
+ For programmer convenience an assembler must also accept the names of
+ 32-bit, 16-bit and 8-bit element tiles which are converted into the
+ corresponding set of 64-bit element tiles.
+*/
+bool
+aarch64_ext_sme_za_list (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int mask = extract_field (self->fields[0], code, 0);
+ info->imm.value = mask;
+ return true;
+}
+
+/* Decode ZA array vector select register (Rv field), optional vector and
+ memory offset (imm4 field).
+*/
+bool
+aarch64_ext_sme_za_array (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int regno = extract_field (self->fields[0], code, 0) + 12;
+ int imm = extract_field (self->fields[1], code, 0);
+ info->za_tile_vector.index.regno = regno;
+ info->za_tile_vector.index.imm = imm;
+ return true;
+}
+
+bool
+aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int regno = extract_field (self->fields[0], code, 0);
+ int imm = extract_field (self->fields[1], code, 0);
+ info->addr.base_regno = regno;
+ info->addr.offset.imm = imm;
+ /* MUL VL operator is always present for this operand. */
+ info->shifter.kind = AARCH64_MOD_MUL_VL;
+ info->shifter.operator_present = (imm != 0);
+ return true;
+}
+
/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
array specifies which field to use for Zn. MM is encoded in the
concatenation of imm5 and SVE_tszh, with imm5 being the less
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "list of 64-bit ZA element tiles"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
}
\f
+/* Instruction bit-fields.
++ Keep synced with 'enum aarch64_field_kind'. */
const aarch64_field fields[] =
{
{ 0, 0 }, /* NIL. */
}
break;
+ case AARCH64_OPND_SME_ADDR_RI_U4xVL:
+ if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
+ {
+ set_offset_out_of_range_error (mismatch_detail, idx, 0, 15);
+ return 0;
+ }
+ break;
+
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
case AARCH64_OPND_SVE_ADDR_RR_LSL3:
+ case AARCH64_OPND_SVE_ADDR_RR_LSL4:
case AARCH64_OPND_SVE_ADDR_RX:
case AARCH64_OPND_SVE_ADDR_RX_LSL1:
case AARCH64_OPND_SVE_ADDR_RX_LSL2:
DEBUG_TRACE ("enter");
- /* Check for cases where a source register needs to be the same as the
- destination register. Do this before matching qualifiers since if
- an instruction has both invalid tying and invalid qualifiers,
- the error about qualifiers would suggest several alternative
- instructions that also have invalid tying. */
i = inst->opcode->tied_operand;
- if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
+
+ if (i > 0)
{
- if (mismatch_detail)
- {
- mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
- mismatch_detail->index = i;
- mismatch_detail->error = NULL;
- }
- return 0;
+ /* Check for tied_operands with specific opcode iclass. */
+ switch (inst->opcode->iclass)
+ {
+ /* For SME LDR and STR instructions #imm must have the same numerical
+ value for both operands.
+ */
+ case sme_ldr:
+ case sme_str:
+ assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
+ assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
+ if (inst->operands[0].za_tile_vector.index.imm
+ != inst->operands[1].addr.offset.imm)
+ {
+ if (mismatch_detail)
+ {
+ mismatch_detail->kind = AARCH64_OPDE_UNTIED_IMMS;
+ mismatch_detail->index = i;
+ }
+ return 0;
+ }
+ break;
+
+ default:
+ /* Check for cases where a source register needs to be the same as the
+ destination register. Do this before matching qualifiers since if
+ an instruction has both invalid tying and invalid qualifiers,
+ the error about qualifiers would suggest several alternative
+ instructions that also have invalid tying. */
+ if (inst->operands[0].reg.regno
+ != inst->operands[i].reg.regno)
+ {
+ if (mismatch_detail)
+ {
+ mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
+ mismatch_detail->index = i;
+ mismatch_detail->error = NULL;
+ }
+ return 0;
+ }
+ break;
+ }
}
/* Match operands' qualifier.
case AARCH64_OPND_SME_ZA_HV_idx_src:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
- snprintf (buf, size, "za%d%c.%s[w%d, %d]",
+ case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
+ snprintf (buf, size, "%sza%d%c.%s[w%d, %d]%s",
+ opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
opnd->za_tile_vector.regno,
opnd->za_tile_vector.v == 1 ? 'v' : 'h',
aarch64_get_qualifier_name (opnd->qualifier),
opnd->za_tile_vector.index.regno,
- opnd->za_tile_vector.index.imm);
+ opnd->za_tile_vector.index.imm,
+ opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
break;
case AARCH64_OPND_SME_list_of_64bit_tiles:
print_sme_za_list (buf, size, opnd->reg.regno);
break;
+ case AARCH64_OPND_SME_ZA_array:
+ snprintf (buf, size, "za[w%d, %d]",
+ opnd->za_tile_vector.index.regno,
+ opnd->za_tile_vector.index.imm);
+ break;
+
case AARCH64_OPND_CRn:
case AARCH64_OPND_CRm:
snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
case AARCH64_OPND_SVE_ADDR_RR_LSL3:
+ case AARCH64_OPND_SVE_ADDR_RR_LSL4:
case AARCH64_OPND_SVE_ADDR_RX:
case AARCH64_OPND_SVE_ADDR_RX_LSL1:
case AARCH64_OPND_SVE_ADDR_RX_LSL2:
case AARCH64_OPND_ADDR_SIMM11:
case AARCH64_OPND_ADDR_SIMM13:
case AARCH64_OPND_ADDR_OFFSET:
+ case AARCH64_OPND_SME_ADDR_RI_U4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
{ \
QLF3(S_D,NIL,NIL), \
}
+#define OP_SVE_QUU \
+{ \
+ QLF3(S_Q,NIL,NIL), \
+}
#define OP_SVE_DUV_BHS \
{ \
QLF3(S_D,NIL,S_B), \
{ \
QLF3(S_D,P_Z,NIL), \
}
+#define OP_SVE_QZU \
+{ \
+ QLF3(S_Q,P_Z,NIL), \
+}
#define OP_SVE_HB \
{ \
QLF2(S_H,S_B), \
SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
+ SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, 0),
+
+ SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, 0, 0),
+ SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, 0, 0),
+ SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, 0, 0),
+ SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, 0, 0),
+ SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QZU, 0, 0),
+
+ SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, 0),
+
+ SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BUU, 0, 0),
+ SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HUU, 0, 0),
+ SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SUU, 0, 0),
+ SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DUU, 0, 0),
+ SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QUU, 0, 0),
+
+ SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
+ SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
+
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \
F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
+ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB, \
+ F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \
(0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \
"an address with a scalar register offset") \
"an SVE predicate register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \
+ Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
+ F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \
+ "an SME horizontal or vertical vector access register") \
+ Y(SVE_REG, sme_za_array, "SME_ZA_array", 0, \
+ F(FLD_SME_Rv,FLD_imm4_2), \
+ "ZA array") \
+ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
+ F(FLD_Rn,FLD_imm4_2), \
+ "memory offset") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
projects / binutils-gdb.git / commitdiff