--- /dev/null
+module test(input [3:0] A, output [3:0] Y1, Y2);
+ assign Y1 = |{A[3], 1'b0, A[1]};
+ assign Y2 = |{A[2], 1'b1, A[0]};
+endmodule
--- /dev/null
+read_verilog constmsk_test.v
+
+copy test gold
+rename test gate
+
+cd gate
+techmap -map constmsk_testmap.v;;
+cd ..
+
+select -assert-count 2 gold/r:A_WIDTH=3
+select -assert-count 1 gate/r:A_WIDTH=2
+select -assert-count 1 gate/c:*
+
+miter -equiv -flatten gold gate miter
+sat -verify -prove trigger 0 miter
--- /dev/null
+(* techmap_celltype = "$reduce_or" *)
+module my_opt_reduce_or(...);
+ parameter A_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ input [A_WIDTH-1:0] A;
+ output reg [Y_WIDTH-1:0] Y;
+
+ parameter _TECHMAP_CONSTMSK_A_ = 0;
+ parameter _TECHMAP_CONSTVAL_A_ = 0;
+
+ wire _TECHMAP_FAIL_ = count_nonconst_bits() == A_WIDTH;
+ wire [1024:0] _TECHMAP_DO_ = "proc;;";
+
+ function integer count_nonconst_bits;
+ integer i;
+ begin
+ count_nonconst_bits = 0;
+ for (i = 0; i < A_WIDTH; i=i+1)
+ if (!_TECHMAP_CONSTMSK_A_[i])
+ count_nonconst_bits = count_nonconst_bits+1;
+ end
+ endfunction
+
+ function has_const_one;
+ integer i;
+ begin
+ has_const_one = 0;
+ for (i = 0; i < A_WIDTH; i=i+1)
+ if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'b1)
+ has_const_one = 1;
+ end
+ endfunction
+
+ integer i;
+ reg [count_nonconst_bits()-1:0] tmp;
+
+ always @* begin
+ if (has_const_one()) begin
+ Y = 1;
+ end else begin
+ for (i = 0; i < A_WIDTH; i=i+1)
+ if (!_TECHMAP_CONSTMSK_A_[i])
+ tmp = {A[i], tmp[count_nonconst_bits()-1:1]};
+ Y = |tmp;
+ end
+ end
+endmodule