ruby: Fixes clock domains in configuration files

This patch fixes scripts related to ruby by adding the ruby clock domain.
Now the L1 controllers and  the Sequencer shares the cpu clock domain,
while the rest of the components use the ruby clock domain.

Before this patch, running simulations with the cpu clock set at 2GHz or
1GHz will output the same time results and could distort power measurements.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 36314fbfb39724c5692031bed0cf5a6b445b6f26..21c80845924dcecfe15d0ad43aa59cf9f3607bcb 100644 (file)
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -105,7 +105,7 @@ system.clk_domain = SrcClockDomain(clock = options.sys_clock,
 #
 # Create the ruby random tester
 #
-system.tester = RubyDirectedTester(requests_to_complete = \
+system.cpu = RubyDirectedTester(requests_to_complete = \
                                    options.requests,
                                    generator = generator)
 

diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 32d5cf34d8c2697bc44901d1e229a8d95ce4c3c1..63faeb97ae48f1a5698768ff70216b3bdb0b8ce1 100644 (file)
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -97,7 +97,7 @@ tester = RubyTester(check_flush = check_flush,
 # actually used by the rubytester, but is included to support the
 # M5 memory size == Ruby memory size checks
 #
-system = System(tester = tester, physmem = SimpleMemory(),
+system = System(cpu = tester, physmem = SimpleMemory(),
                 mem_ranges = [AddrRange(options.mem_size)])
 
 # Create a top-level voltage domain and clock domain

diff --git a/configs/example/se.py b/configs/example/se.py
index c6b98ec0e965ad78767e1ddc40c93eea685433cd..ad15e14b517a6ef1bcd3f7039b528549472f9470 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -235,6 +235,8 @@ if options.ruby:
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ports))
 
+    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
     for i in xrange(np):
         ruby_port = system.ruby._cpu_ports[i]
 

diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py
index 966c801727cdea14a495e9b8c8c1f22fc8dd7a90..ee6ceccf9f0fb276b6910533756a77ecb94b07d5 100644 (file)
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -102,9 +102,11 @@ def create_system(options, system, dma_ports, ruby_system):
             l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
                           Icache = l0i_cache, Dcache = l0d_cache,
                           send_evictions = (options.cpu_type == "detailed"),
+                          clk_domain=system.cpu[i].clk_domain,
                           ruby_system = ruby_system)
 
             cpu_seq = RubySequencer(version = i, icache = l0i_cache,
+                        clk_domain=system.cpu[i].clk_domain,
                         dcache = l0d_cache, ruby_system = ruby_system)
 
             l0_cntrl.sequencer = cpu_seq

diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 845d5cf2215110e9e8e0967b78ea16ef9d156ea9..c70c599c7a45df205f4124d3da23965c6f401ccc 100644 (file)
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -95,12 +95,14 @@ def create_system(options, system, dma_ports, ruby_system):
                                           options.cpu_type == "detailed"),
                                       prefetcher = prefetcher,
                                       ruby_system = ruby_system,
+                                      clk_domain=system.cpu[i].clk_domain,
                                       transitions_per_cycle=options.ports,
                                       enable_prefetch = False)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
+                                clk_domain=system.cpu[i].clk_domain,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq

diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 9fb6ca3661e2ad7c801e56890506bdb1a7d5359f..0124792506f787b6f0990afa1af3ec1ae9d07471 100644 (file)
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -82,11 +82,13 @@ def create_system(options, system, dma_ports, ruby_system):
                                       send_evictions = (
                                           options.cpu_type == "detailed"),
                                       transitions_per_cycle = options.ports,
+                                      clk_domain=system.cpu[i].clk_domain,
                                       ruby_system = ruby_system)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = cache,
                                 dcache = cache,
+                                clk_domain=system.cpu[i].clk_domain,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq

diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index a7de3bf8f55933397c703bdb03c596e61ac971d5..aa474209ff859a6b3708e56144319f303cb1afc5 100644 (file)
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -92,11 +92,13 @@ def create_system(options, system, dma_ports, ruby_system):
                                       send_evictions = (
                                           options.cpu_type == "detailed"),
                                       transitions_per_cycle = options.ports,
+                                      clk_domain=system.cpu[i].clk_domain,
                                       ruby_system = ruby_system)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
+                                clk_domain=system.cpu[i].clk_domain,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq

diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 52c1b44f4eeb82f14343968f09158a479c3ae581..36a5325749a6b16b3ca956348b393613c559058c 100644 (file)
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -112,11 +112,13 @@ def create_system(options, system, dma_ports, ruby_system):
                                       send_evictions = (
                                           options.cpu_type == "detailed"),
                                       transitions_per_cycle = options.ports,
+                                      clk_domain=system.cpu[i].clk_domain,
                                       ruby_system = ruby_system)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
+                                clk_domain=system.cpu[i].clk_domain,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index eaa3bc7a2beab5a13d9dee4269cbbbdcb8897466..de98fd0c2a4dc39f18d999915eff6ee598de5467 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -105,11 +105,13 @@ def create_system(options, system, dma_ports, ruby_system):
                                       send_evictions = (
                                           options.cpu_type == "detailed"),
                                       transitions_per_cycle = options.ports,
+                                      clk_domain=system.cpu[i].clk_domain,
                                       ruby_system = ruby_system)
 
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
+                                clk_domain=system.cpu[i].clk_domain,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index f2c88c92b654f5287859d39e8a9e6b0fba07d953..b3d3f036320ec4d25902f0a9413b7d0aeb5c6971 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -78,7 +78,10 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
 tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
                     wakeup_frequency = 10, num_cpus = options.num_cpus)
 
-system = System(tester = tester, physmem = SimpleMemory(null = True))
+# We set the testers as cpu for ruby to find the correct clock domains
+# for the L1 Objects.
+system = System(cpu = tester, physmem = SimpleMemory(null = True))
+
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = '1GHz',