CacheMemory: add allocateVoid() that is == allocate() but no return value.

This function duplicates the functionality of allocate() exactly, except that it does not return
a return value.  In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable.  This is kind of a hack to get around
those issues, but suggestions welcome.

diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 7d444ab572fda14fd4cc9efa1b9666f5a1b97f1c..cf0f64500bb0476160cc04639f1686ac0ec62583 100644 (file)
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -134,6 +134,7 @@ structure (CacheMemory, external = "yes") {
   bool cacheAvail(Address);
   Address cacheProbe(Address);
   AbstractCacheEntry allocate(Address, AbstractCacheEntry);
+  void allocateVoid(Address, AbstractCacheEntry);
   void deallocate(Address);
   AbstractCacheEntry lookup(Address);
   bool isTagPresent(Address);

diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 197ac9f401d0d3a0cbe5cc106c31e8d25a18ac6e..e2e9a429e90ad2eb4cdf5fc0f94ccc6961f00d68 100644 (file)
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -83,6 +83,10 @@ class CacheMemory : public SimObject
 
     // find an unused entry and sets the tag appropriate for the address
     AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
+    void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
+    {
+        allocate(address, new_entry);
+    }
 
     // Explicitly free up this address
     void deallocate(const Address& address);

diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh
index 1404f55611abeecd4b6640abc93e094cee14ab24..b34488fb129ca175d70e3d25a2ca36f2f8a8318f 100644 (file)
--- a/src/mem/ruby/system/WireBuffer.hh
+++ b/src/mem/ruby/system/WireBuffer.hh
@@ -54,7 +54,7 @@
 /////////////////////////////////////////////////////////////////////////////
 
 class Consumer;
-class Message;  // I added this and removed Message.hh
+class Message; 
 
 class WireBuffer : public SimObject
 {
@@ -88,7 +88,6 @@ class WireBuffer : public SimObject
     void clearStats() const;
     void printStats(std::ostream& out) const;
 
-//    int m_dummy;
     uint64_t m_msg_counter;
 
   private:

diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py
index 0bcc291bbe2d16827655c6e14a2aeeada63ad07e..bca19b4dfd093aff56089f4ab5b76ef75a3741ab 100644 (file)
--- a/src/mem/ruby/system/WireBuffer.py
+++ b/src/mem/ruby/system/WireBuffer.py
@@ -28,7 +28,6 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-#from Controller import RubyController
 
 class RubyWireBuffer(SimObject):
     type = 'RubyWireBuffer'