Fix sign extension when sign is 1'bx

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a09f4a0d1cbfa81cb2edbf69a06f605684b95a63..95a24c93f90b4ffd46addbe4e4511ffdeefca1b8 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 
        if (width_ < width) {
                RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
-               if (!is_signed)
+               if (padding != RTLIL::State::Sx && !is_signed)
                        padding = RTLIL::State::S0;
                while (width_ < width)
                        append(padding);