MemorySystem: Fix the use of ?: to produce correct results.

--HG--
extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 42c4431bba4c3f2434714f92702db7cacb3aa0d3..620e2ac607b1198fa57c6a4a691d87102f18a785 100644 (file)
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -148,10 +148,7 @@ void Bus::occupyBus(PacketPtr pkt)
 
     // The first word will be delivered after the current tick, the delivery
     // of the address if any, and one bus cycle to deliver the data
-    pkt->firstWordTime =
-        tickNextIdle +
-        pkt->isRequest() ? clock : 0 +
-        clock;
+    pkt->firstWordTime = tickNextIdle + (pkt->isRequest() ? clock : 0) + clock;
 
     //Advance it numCycles bus cycles.
     //XXX Should this use the repeated addition trick as well?

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 402e34db2104b96df3fdea11415bfc1322c21305..02e951df4124e9424bf938a36241e107a45b7ac4 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -736,7 +736,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
 
                 // If critical word (no offset) return first word time
                 completion_time = tags->getHitLatency() +
-                    transfer_offset ? pkt->finishTime : pkt->firstWordTime;
+                    (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
 
                 assert(!target->pkt->req->isUncacheable());
                 missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=

diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 7796773a398aeabf5b01d09d8d3568f5aa7fa34e..4e9b984818bf5d78665bcf85a82bb39974032566 100644 (file)
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -263,7 +263,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
     if (targets->needsExclusive || pkt->needsExclusive()) {
         // actual target device (typ. PhysicalMemory) will delete the
         // packet on reception, so we need to save a copy here
-        PacketPtr cp_pkt = new Packet(pkt);
+        PacketPtr cp_pkt = new Packet(pkt, true);
         targets->add(cp_pkt, curTick, _order, false);
         ++ntargets;
 

diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index b1a6a48131cfa3f3c5ae4856b6c61ac0c70bd9c3..9fa27046b30b52374788131bddf78b29a4401477 100644 (file)
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -95,6 +95,7 @@ void
 SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
 {
     assert(when > curTick);
+    assert(when < curTick + Clock::Int::ms);
 
     // Nothing is on the list: add it and schedule an event
     if (transmitList.empty() || when < transmitList.front().tick) {