clear persist bit if setvl explicitly called

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 03249f7100b772773692d8997730980cec60e2ed..bdf792f2d8ae851023ccc704267de7781e736c03 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -49,7 +49,9 @@ Pseudo-code:
         SVSTATE[7:13] <- VL
         if _RT != 0b00000 then
            GPR(_RT) <- [0]*57 || VL
+        # set requested Vertical-First mode, clear persist
         SVSTATE[63] <- vf
+        SVSTATE[62] <- 0b0
 
 Special Registers Altered:
 
@@ -161,7 +163,7 @@ Pseudo-code:
         # set up FRB and FRS
         SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
         SVSHAPE0[30:31] <- 0b01          # DCT/FFT mode
-        if (SVRM = 0b0100) then
+        #if (SVRM = 0b0100) then
         SVSHAPE0[6:11] <- 0b000001       # DCT Inner Butterfly mode
         SVSHAPE0[18:20] <- 0b001         # DCT Inner Butterfly sub-mode
         SVSHAPE0[21:23] <- 0b001         # "inverse" on outer loop