unsigned bs_size;
struct rvid_buffer dpb;
+ bool use_legacy;
};
/* flush IB to the hardware */
reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain,
RADEON_PRIO_MIN);
- set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
- set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
+ if (!dec->use_legacy) {
+ uint64_t addr;
+ addr = dec->ws->buffer_get_virtual_address(cs_buf);
+ addr = addr + off;
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
+ } else {
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
+ }
set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
}
if (!dec)
return NULL;
+ if (info.drm_major < 3)
+ dec->use_legacy = TRUE;
+
dec->base = *templ;
dec->base.context = context;
dec->base.width = width;