i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.

In gen6 the geometry shader payload includes the PrimitiveID information in
r0.1. When the shader code uses glPimitiveIdIn we will have to move this to
a separate hardware register where we can map this attribute. This opcode
takes the selected destination register and moves r0.1 there.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 1e5a12b6a06c11ca943e10ebdb0dcfc473300b36..e359c4509b7a28fe6031ef209d814eddfd6df0cd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1035,6 +1035,14 @@ enum opcode {
     * the header in the URB write operation we are allocating the handle for.
     */
    GS_OPCODE_FF_SYNC,
+
+   /**
+    * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
+    * register.
+    *
+    * - dst is the GRF where PrimitiveID information will be moved.
+    */
+   GS_OPCODE_SET_PRIMITIVE_ID,
 };
 
 enum brw_derivative_quality {

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 1c8bdb6ecd9c3ea6eecbfecc3e6c2032e389d624..e4c394878822c1a6fa150f2bc0427a2fd4bc4d65 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -526,6 +526,8 @@ brw_instruction_name(enum opcode op)
       return "get_instance_id";
    case GS_OPCODE_FF_SYNC:
       return "ff_sync";
+   case GS_OPCODE_SET_PRIMITIVE_ID:
+      return "set_primitive_id";
 
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 47045e7bc3c60172c065fa3b1faaac4a929e4c02..f2ec26a566f428d0db3ffa214064e8bff16c41c7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -661,6 +661,7 @@ private:
    void generate_gs_ff_sync(vec4_instruction *inst,
                             struct brw_reg dst,
                             struct brw_reg src0);
+   void generate_gs_set_primitive_id(struct brw_reg dst);
    void generate_oword_dual_block_offsets(struct brw_reg m1,
                                          struct brw_reg index);
    void generate_scratch_write(vec4_instruction *inst,

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 168536cd5e22a6a7fb089fe9eed7d49e0ee46cda..c2d0d2ecbed6c94ef6a9993a87b68d9e4762b798 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -721,6 +721,18 @@ vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
    brw_pop_insn_state(p);
 }
 
+void
+vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
+{
+   /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
+   struct brw_reg src = brw_vec8_grf(0, 0);
+   brw_push_insn_state(p);
+   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+   brw_set_default_access_mode(p, BRW_ALIGN_1);
+   brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
+   brw_pop_insn_state(p);
+}
+
 void
 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
                                                   struct brw_reg index)
@@ -1351,6 +1363,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_gs_ff_sync(inst, dst, src[0]);
          break;
 
+      case GS_OPCODE_SET_PRIMITIVE_ID:
+         generate_gs_set_primitive_id(dst);
+         break;
+
       case GS_OPCODE_SET_DWORD_2:
          generate_gs_set_dword_2(dst, src[0]);
          break;