hdl.xfrm: transform drivers as well in DomainRenamer.

This is necessary because drivers may be late bound.

Fixes #304.

diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py
index 882ae94b6dc9e2902cb302732f62215617d24088..75f85ba6a24be76746ceb1418ea9c425c159ff8d 100644 (file)
--- a/nmigen/hdl/xfrm.py
+++ b/nmigen/hdl/xfrm.py
@@ -482,7 +482,7 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
             if domain in self.domain_map:
                 domain = self.domain_map[domain]
             for signal in signals:
-                new_fragment.add_driver(signal, domain)
+                new_fragment.add_driver(self.on_value(signal), domain)
 
 
 class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer):

diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index fc4d0fe0eeb3ecb05621c6ed42f934dd93ae419a..4685523b93ed675b96b7dbefa97daeffdf242200 100644 (file)
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -389,6 +389,25 @@ class FragmentDomainsTestCase(FHDLTestCase):
                     "domains explicitly, or give distinct names to subfragments"):
             f._propagate_domains_up()
 
+    def test_domain_conflict_rename_drivers(self):
+        cda = ClockDomain("sync")
+        cdb = ClockDomain("sync")
+
+        fa = Fragment()
+        fa.add_domains(cda)
+        fb = Fragment()
+        fb.add_domains(cdb)
+        fb.add_driver(ResetSignal("sync"), None)
+        f = Fragment()
+        f.add_subfragment(fa, "a")
+        f.add_subfragment(fb, "b")
+
+        f._propagate_domains_up()
+        fb_new, _ = f.subfragments[1]
+        self.assertEqual(fb_new.drivers, OrderedDict({
+            None: SignalSet((ResetSignal("b_sync"),))
+        }))
+
     def test_propagate_down(self):
         cd = ClockDomain()