compiler: add shader_info.vs.blit_sgprs_amd

for internal radeonsi shaders

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 115dd01e2b904b9b11bc9a7e6e0e0bb5d4f82ce1..15150aa9b2e0f060ad01e403965455c72c0d57eb 100644 (file)
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -158,6 +158,13 @@ typedef struct shader_info {
          /* Which inputs are doubles */
          uint64_t double_inputs;
 
+         /* For AMD-specific driver-internal shaders. It replaces vertex
+          * buffer loads with code generating VS inputs from scalar registers.
+          *
+          * Valid values: SI_VS_BLIT_SGPRS_POS_*
+          */
+         unsigned blit_sgprs_amd;
+
          /* True if the shader writes position in window space coordinates pre-transform */
          bool window_space_position;
       } vs;

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 4770e8f479086926624f26bd10761f53ece26c88..ca805df8739400ddfcb87c40be92b47acd73a351 100644 (file)
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -2106,6 +2106,9 @@ ttn_compile_init(const void *tgsi_tokens,
       case TGSI_PROPERTY_NEXT_SHADER:
          s->info.next_stage = tgsi_processor_to_shader_stage(value);
          break;
+      case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
+         s->info.vs.blit_sgprs_amd = value;
+         break;
       default:
          if (value) {
             fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index ebeaa631e8a7365c15dab62917a4e360ebc1395a..0f3a11268f710e4f7d2c4226c5b369578ce17bb7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -424,6 +424,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
        if (nir->info.stage == MESA_SHADER_VERTEX) {
                info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
                        nir->info.vs.window_space_position;
+               info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
+                       nir->info.vs.blit_sgprs_amd;
        }
 
        if (nir->info.stage == MESA_SHADER_TESS_CTRL) {