Add cleaning pass

diff --git a/gram/simulation/simsoc.ys b/gram/simulation/simsoc.ys
index bdd7d3ddc8235571bbfb3760c6ef9662275ac113..2394c3881f98b9e6ee73eb4b3ca1a3d3ea537ddb 100644 (file)
--- a/gram/simulation/simsoc.ys
+++ b/gram/simulation/simsoc.ys
@@ -17,4 +17,5 @@ flatten \decoder
 flatten \arbiter
 flatten \sysclk
 opt -fine -full
+clean
 write_verilog -norename build_simsoc/top.v