Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b

diff --cc src/cpu/base.cc
Simple merge

diff --cc src/cpu/base.hh
index 79d22c9927392af2bd79454d543292943c2b0370,df665ed2327fa9877de22c8b945656a0e0361389..9257778ef7f30030bc44750c511daadba13ed9c5
--- 1/src/cpu/base.hh
--- 2/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@@ -77,11 -73,24 +77,25 @@@ class BaseCPU : public MemObjec
      inline Tick cycles(int numCycles) const { return clock * numCycles; }
      inline Tick curCycle() const { return curTick / clock; }
  
+     /** The next cycle the CPU should be scheduled, given a cache
+      * access or quiesce event returning on this cycle.  This function
+      * may return curTick if the CPU should run on the current cycle.
+      */
+     Tick nextCycle();
+ 
+     /** The next cycle the CPU should be scheduled, given a cache
+      * access or quiesce event returning on the given Tick.  This
+      * function may return curTick if the CPU should run on the
+      * current cycle.
+      * @param begin_tick The tick that the event is completing on.
+      */
+     Tick nextCycle(Tick begin_tick);
+ 
  #if FULL_SYSTEM
    protected:
 -    uint64_t interrupts[TheISA::NumInterruptLevels];
 -    uint64_t intstatus;
 +//    uint64_t interrupts[TheISA::NumInterruptLevels];
 +//    uint64_t intstatus;
 +    TheISA::Interrupts interrupts;
  
    public:
      virtual void post_interrupt(int int_num, int index);

diff --cc src/dev/isa_fake.hh
Simple merge