(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 60d02997a85eb9541085509ba42c25df4b4bd76c..24c4d4eb6401e5d9010cf1f51bd4f4e43f1a98c7 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -361,3 +361,20 @@ Software Driver development and debugging is dramatically simplified.
 Which brings us to the next important question: how is any of these
 CPU-centric Vector-centric improvements relevant to power efficiency
 and making more effective use of resources?
+
+# Simpler more compact programs
+
+The first and most obvious saving is that, just as with any Vector
+ISA, the amount of data processing requested
+and controlled by each instruction is enormous, and leaves the
+Decode and Issue Engines idle, as well as the L1 I-Cache. With
+programs being smaller, chances are higher that they fit into
+L1 Cache, or that the L1 Cache may be made smaller.
+
+Even a Packed SIMD ISA could take limited advantage of a higher
+bang-per-buck for limited specific workloads, as long as the
+stripmining setup and teardown is not required.  However a
+2-wide Packed SIMD instruction is nowhere near as high a bang-per-buck
+ratio as a 64-wide Vector Length.
+
+Realistically,