targets/icebreaker: create CRG after SoC.

diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py
index b8045b0cffbc1bf1701ee77860351465889d542f..f58827a11ea5882b1a0a02f5e860b2008e6c792e 100755 (executable)
--- a/litex/boards/targets/icebreaker.py
+++ b/litex/boards/targets/icebreaker.py
@@ -71,12 +71,12 @@ class BaseSoC(SoCCore):
         # Set CPU variant / reset address
         kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
 
-        # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=64*kB)
         self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)