SPARC: Truncate syscall args and return values appropriately.

diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh
index cf13fc3e8f9a9cb5f4b2dc5f61055bbe3d5ffd7c..d4e6c7c509302c6a54be9ca5fd4a4639f02084c5 100644 (file)
--- a/src/arch/sparc/syscallreturn.hh
+++ b/src/arch/sparc/syscallreturn.hh
@@ -50,13 +50,23 @@ namespace SparcISA
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
             //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
-            tc->setIntReg(ReturnValueReg, return_value.value());
+            IntReg val = return_value.value();
+            if (bits(tc->readMiscRegNoEffect(
+                            SparcISA::MISCREG_PSTATE), 3, 3)) {
+                val = bits(val, 31, 0);
+            }
+            tc->setIntReg(ReturnValueReg, val);
         } else {
             // got an error, set XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) | 0x11);
             //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
-            tc->setIntReg(ReturnValueReg, -return_value.value());
+            IntReg val = -return_value.value();
+            if (bits(tc->readMiscRegNoEffect(
+                            SparcISA::MISCREG_PSTATE), 3, 3)) {
+                val = bits(val, 31, 0);
+            }
+            tc->setIntReg(ReturnValueReg, val);
         }
     }
 };

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index a503ab600930b654f0141a5475505511883b6d05..4831b701a3e1cba12851c5aa50b71ceac0a01b91 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -385,8 +385,15 @@ class SimpleThread : public ThreadState
     TheISA::IntReg getSyscallArg(int i)
     {
         assert(i < TheISA::NumArgumentRegs);
-        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg[i]));
+        TheISA::IntReg val = regs.readIntReg(
+                TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
+#if THE_ISA == SPARC_ISA
+        if (bits(this->readMiscRegNoEffect(
+                        SparcISA::MISCREG_PSTATE), 3, 3)) {
+            val = bits(val, 31, 0);
+        }
+#endif
+        return val;
     }
 
     // used to shift args for indirect syscall