Added Verilog support for "`default_nettype none"

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 56e9393b7c7f12bc7cf6ce88731720e7d6f06524..58be067910d04ca0c4a7b11e939295e454ba013d 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -46,7 +46,7 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-       bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
+       bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
        AstNode *current_ast, *current_ast_mod;
        std::map<std::string, AstNode*> current_scope;
        RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@@ -836,11 +836,12 @@ static AstModule* process_module(AstNode *ast, bool defer)
        current_module->lib = flag_lib;
        current_module->noopt = flag_noopt;
        current_module->icells = flag_icells;
+       current_module->autowire = flag_autowire;
        return current_module;
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
 {
        current_ast = ast;
        flag_dump_ast1 = dump_ast1;
@@ -852,6 +853,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
        flag_lib = lib;
        flag_noopt = noopt;
        flag_icells = icells;
+       flag_autowire = autowire;
 
        assert(current_ast->type == AST_DESIGN);
        for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
@@ -897,6 +899,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
        flag_lib = lib;
        flag_noopt = noopt;
        flag_icells = icells;
+       flag_autowire = autowire;
        use_internal_line_num();
 
        std::string para_info;
@@ -986,6 +989,7 @@ RTLIL::Module *AstModule::clone() const
        new_mod->lib = lib;
        new_mod->noopt = noopt;
        new_mod->icells = icells;
+       new_mod->autowire = autowire;
 
        return new_mod;
 }

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index f42bc35fb513e3025210c06b009d1a401357d76d..72a2a4600ded4198e4ac5d5250931361e153a8b2 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -238,13 +238,13 @@ namespace AST
        };
 
        // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-       void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false, bool defer = true);
+       void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 
        // parametric modules are supported directly by the AST library
        // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
        struct AstModule : RTLIL::Module {
                AstNode *ast;
-               bool nolatches, nomem2reg, mem2reg, lib, noopt, icells;
+               bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire;
                virtual ~AstModule();
                virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
                virtual RTLIL::Module *clone() const;
@@ -265,7 +265,7 @@ namespace AST
 namespace AST_INTERNAL
 {
        // internal state variables
-       extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
+       extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
        extern AST::AstNode *current_ast, *current_ast_mod;
        extern std::map<std::string, AST::AstNode*> current_scope;
        extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 12fe23fd83bcc471b7a51e8ad4b85907e37b4efe..bc3783bda202268c233ab6118b65527ca34542df 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -921,7 +921,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                RTLIL::Wire *wire = new RTLIL::Wire;
                                wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
                                wire->name = str;
-                               log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+                               if (flag_autowire)
+                                       log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+                               else
+                                       log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
                                current_module->wires[str] = wire;
                        }
                        else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {

diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 81167cf4eccd3d6e3b5e0811750cd58717c0c120..79f44b4a6d1c5f8b8f19a0921682bb11640cc95a 100644 (file)
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -81,6 +81,18 @@ namespace VERILOG_FRONTEND {
 
 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 
+"`default_nettype"[ \t]+[^ \t\r\n/]+ {
+       char *p = yytext;
+       while (*p != 0 && *p != ' ' && *p != '\t') p++;
+       while (*p == ' ' || *p == '\t') p++;
+       if (!strcmp(p, "none"))
+               VERILOG_FRONTEND::default_nettype_wire = false;
+       else if (!strcmp(p, "wire"))
+               VERILOG_FRONTEND::default_nettype_wire = true;
+       else
+               frontend_verilog_yyerror("Unsupported default nettype: %s", p);
+}
+
 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
        frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 }

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 8080729b0c97af7d663f5d06cc6fc51b61834638..4726f1aa3688e4f6e2bc8fc36ccee20ae51564a5 100644 (file)
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
        struct AstNode *current_ast, *current_ast_mod;
        int current_function_or_task_port_id;
        std::vector<char> case_type_stack;
+       bool default_nettype_wire;
 }
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index db53e8c68eea130d63ee6b56f6f83249651208ba..873ae3d51ff334df72d3963bf4b384df46104e5e 100644 (file)
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -373,7 +373,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
                }
 
                if (tok == "`timescale") {
-                       std::string name;
                        skip_spaces();
                        while (!tok.empty() && tok != "\n")
                                tok = next_token(true);

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 477f26b45d950831364d627151287d28b43adc4a..13c2676dbf32a98141fb34b7466ac3958fad7294 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -256,6 +256,7 @@ struct VerilogFrontend : public Frontend {
                AST::get_line_num = &frontend_verilog_yyget_lineno;
 
                current_ast = new AST::AstNode(AST::AST_DESIGN);
+               default_nettype_wire = true;
 
                FILE *fp = f;
                std::string code_after_preproc;
@@ -279,7 +280,7 @@ struct VerilogFrontend : public Frontend {
                                        child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
                }
 
-               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer);
+               AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
 
                if (!flag_nopp)
                        fclose(fp);

diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 8b4fae6e97fb04538c4b2e12bfcee463f0b7a0d4..99b2164efe8a19ef81d4ccf50be1e5c576a350bd 100644 (file)
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -42,6 +42,9 @@ namespace VERILOG_FRONTEND
 
        // this function converts a Verilog constant to an AST_CONSTANT node
        AST::AstNode *const2ast(std::string code, char case_type = 0);
+
+       // state of `default_nettype
+       extern bool default_nettype_wire;
 }
 
 // the pre-processor