re PR target/71297 (ICE on invalid code in altivec_resolve_overloaded_builtin (rs6000...

[gcc]

2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/71297
	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Allow standard error handling to take over when a wrong number
	of arguments is presented to __builtin_vec_ld () or
	__builtin_vec_st ().

[gcc/testsuite]

2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/71297
	* gcc.target/powerpc/pr71297.c: New.

From-SVN: r238168

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1cde33269309087761da75bb4e2ce5d1af36eccd..9897bfce6562cfab8fbf792369a55da843757af5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       PR target/71297
+       * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
+       Allow standard error handling to take over when a wrong number
+       of arguments is presented to __builtin_vec_ld () or
+       __builtin_vec_st ().
+
 2016-07-08  Jiong Wang  <jiong.wang@arm.com>
 
        * config/aarch64/aarch64-simd-builtins.def (smax): Remove float

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4500668ed9f5868302a545fbb3fc884ebcdce5d2..fe6db2c097a49d0ec4e00e9e077f5996b42631fc 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -5281,10 +5281,11 @@ assignment for unaligned loads and stores");
      are able to honor __restrict__, for example.  We may want to
      consider this for all memory access built-ins.
 
-     When -maltivec=be is specified, simply punt to existing
-     built-in processing.  */
+     When -maltivec=be is specified, or the wrong number of arguments
+     is provided, simply punt to existing built-in processing.  */
   if (fcode == ALTIVEC_BUILTIN_VEC_LD
-      && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG))
+      && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
+      && nargs == 2)
     {
       tree arg0 = (*arglist)[0];
       tree arg1 = (*arglist)[1];
@@ -5354,7 +5355,8 @@ assignment for unaligned loads and stores");
 
   /* Similarly for stvx.  */
   if (fcode == ALTIVEC_BUILTIN_VEC_ST
-      && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG))
+      && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
+      && nargs == 3)
     {
       tree arg0 = (*arglist)[0];
       tree arg1 = (*arglist)[1];

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0cbcb8896a216895c031e702350d7733885877b5..4f107b1af518c3afef2e89f7dbfd5a2c6ca89343 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-07-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       PR target/71297
+       * gcc.target/powerpc/pr71297.c: New.
+
 2016-07-08  Jiong Wang  <jiong.wang@arm.com>
 
        * gcc.target/aarch64/simd/vminmaxnm_1.c: New.

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71297.c b/gcc/testsuite/gcc.target/powerpc/pr71297.c
new file mode 100644 (file)
index 0000000..db1aaf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr71297.c
@@ -0,0 +1,10 @@
+/* PR target/71763 */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+
+int main ()
+{
+  __builtin_vec_st (); /* { dg-error "too few arguments to function" } */
+
+}
+