# map internal cells to FPGA cells
techmap -map ../cells.v; opt
+# insert clock buffers
+select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d
+iopadmap -inpad BUFGP O:I @clocks
+
# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad BUFGP O:I
+iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n
# write netlist
write_edif synth.edif
-module top(clk, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
+module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-input clk;
+input clk, ctrl;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
reg [31:0] counter;
always @(posedge clk)
- counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
+ counter <= counter + (ctrl ? 4 : 1);
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;