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Add to CHANGELOG
authorEddie Hung <eddie@fpgeh.com>
Thu, 6 Jun 2019 19:04:42 +0000 (12:04 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 6 Jun 2019 19:04:42 +0000 (12:04 -0700)
CHANGELOG patch | blob | history

diff --git a/CHANGELOG b/CHANGELOG
index 36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb..e67d9c9032bf06db4b2a38cac486fbd380c43da5 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - Added "muxpack" pass
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"