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diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5db0afeea04e6ba61a4fb135605a1c42721bd077..67ced5ea9fa70eca349c0031a691b4d703af6b9c 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -608,6 +608,8 @@ sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
     // normally the result is shuffled down by 32 bits (elwidth==default)
     // however with variable bitwidth we want the top elwidth bits,
     // using the SOURCE registers to determine that width.
+    // specifically: truncation of the result due to a shorter
+    // destination elwidth is NOT our problem.
     uint8_t bitwidth = _insn->src_bitwidth;
     uint64_t vlhs = 0;
     uint64_t vrhs = 0;